Patents by Inventor Sheng FU

Sheng FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240138678
    Abstract: The present invention discloses a highly reliable implantable device of an implantable biological sensor. Before use, the fixed seat cannot move relative to the slidable seat, achieving reliable transportation. In use, the lower end face of the slidable seat is pressed against the skin; the lower end face of the first snap-fit protrusion squeezes the upper end face of the vertical snap-fit plate; the first snap-fit protrusion is gradually away from the support of the vertical snap-fit plate, whereby the inside vertical face of the vertical snap-fit plate pushes the first snap-fit protrusion inward, and the fixed seat moves downward relative to the slidable seat, achieving good controllability.
    Type: Application
    Filed: May 4, 2023
    Publication date: May 2, 2024
    Inventors: Dan Yan, Sheng Fu, Guanhua Li, Zhe Zhang, Qinglong Dong
  • Publication number: 20240121685
    Abstract: A method of reducing gray energy consumption and achieving optimal gray energy saving for carbon neutralization is proposed. In a cellular network, each cell or BS (group of cells) has renewable (green) and non-renewable (gray, on-grid power) energy sources. The renewable (green) energy is highly variable and unpredictable, while non-renewable (gray, on-grid power) is stable but is not renewable and thus has more carbon impact. Each cell or BS (group of cells) services is associated UEs when it is on. In one novel aspect, a cell or BS (group of cells) that consumes more non-renewable energy can give some or all of its served UEs to another cell or BS (group of cells) that consumes less non-renewable energy.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 11, 2024
    Inventors: Chien-Sheng Yang, I-Kang Fu, YUAN-CHIEH LIN, Chia-Lin Lai, Yu-Hsin Lin, Yun-Hsuan Chang
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20240093585
    Abstract: A fracturing apparatus is provided. The fracturing apparatus includes a plunger pump, a transmission shaft, a main motor, an oil pipe, a first radiator and a noise reduction cabin. The main motor is spaced apart from the plunger pump, the plunger pump is connected with the main motor through the transmission shaft; the oil pipe is configured to be connected with the plunger pump; the first radiator is spaced apart from the plunger pump, the first radiator is configured to dissipate heat from oil in the oil pipe, the main motor, the first radiator and at least part of the oil pipe are all located inside the noise reduction cabin, and the plunger pump is located outside the noise reduction cabin.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shanwu FU, Ruijie DU, Jian ZHANG, Jifeng ZHONG, Sheng CHANG, Xiaolei JI
  • Patent number: 11935728
    Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Cheng Wu, Sheng-Ying Wu, Ming-Hsien Lin, Chun Fu Chen
  • Publication number: 20240085634
    Abstract: An optical fiber transmission device includes a substrate, a photonic integrated circuit, and an optical fiber assembly. The photonic integrated circuit is disposed on an area of the substrate. The substrate has a protruding structure at an interface with an edge of the photonic integrated circuit. The optical fiber assembly includes an optical fiber and a ferrule that sleeves the optical fiber. The protruding structure of the substrate is configured to abut against the ferrule to limit the position of the optical fiber assembly in a vertical direction of the substrate, such that the protruding structure is a stopper for the optical fiber assembly in the vertical direction.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 14, 2024
    Applicant: AuthenX Inc.
    Inventors: Chun-Chiang YEN, Po-Kuan SHEN, Sheng-Fu LIN, Yi-Ting LU, Jun-Rong CHEN, Jenq-Yang CHANG, Mao-Jen WU
  • Publication number: 20240089000
    Abstract: An optical fiber network device includes a fiber and a photonic integrated circuit. Fiber receives a first optical signal and transmits a second optical signal. A first wavelength of first optical signal is different from a second wavelength of second optical signal. Photonic integrated circuit includes a laser chip, a photodetector, a wavelength division multiplexing coupler, a first optical modulation element and a second optical modulation element. Laser chip is disposed on photonic integrated circuit, and is configured to generate first optical signal. Photodetector detects second optical signal. Wavelength division multiplexing coupler is configured to couple first optical signal to fiber, and receives second optical signal. First optical modulation element is coupled to wavelength division multiplexing coupler and laser chip, and is configured to modulate first optical signal.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 14, 2024
    Applicant: AuthenX Inc.
    Inventors: Sheng-Fu LIN, Po-Kuan SHEN, Chun-Chiang YEN, Yi-Ting LU, Jun-Rong CHEN, Jenq-Yang CHANG, Mao-Jen WU
  • Publication number: 20240087960
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
  • Patent number: 11916060
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Publication number: 20240047395
    Abstract: A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
  • Publication number: 20240030215
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Publication number: 20230395592
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Hsiao-Ching Huang, Hao-Hua Hsu, Sheng-Fu Hsu
  • Publication number: 20230361021
    Abstract: A semiconductor interconnection structure includes a lower inter-level dielectric layer located above a substrate, a lower metal via located in the lower inter-level dielectric layer, a first horizontal dielectric layer located over the lower inter-level dielectric layer and the lower metal via, an upper inter-level dielectric layer located over the first horizontal dielectric layer and having a dielectric constant smaller than that of the first horizontal dielectric layer, an upper metal via located in the upper inter-level dielectric layer and the first horizontal dielectric layer, and electrically connected to the lower metal via, a diffusion barrier layer located around the upper metal via, and located between the upper inter-level dielectric layer and the upper metal via; and a dielectric sidewall located the diffusion barrier layer and the upper inter-level dielectric layer.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Inventor: Sheng-Fu HUANG
  • Patent number: 11804482
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate of a first type, a first doped region embedded within the substrate and having a first portion and a second portion, and a first gate electrode disposed above the substrate. The semiconductor device further comprises a well region of a second type and embedded within the substrate. The well region is in contact with the second portion of the first doped region.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Fu Hsu, Hsiao-Ching Huang
  • Publication number: 20230341630
    Abstract: An optical network device includes a substrate, a photonic integrated circuit, a fiber, and a packaging cap. Photonic integrated circuit is disposed on substrate. Fiber is configured to receive a first optical signal and transmit a second optical signal. A first wavelength of first optical signal is different from a second wavelength of second optical signal. Packaging cap is configured to combine fiber with substrate, and is configured to cover photonic integrated circuit and fix fiber, so as to align fiber with photonic integrated circuit, so that an oblique angle is formed between a normal vector of a plane where photonic integrated circuit is located and a direction in which fiber extends. Photonic integrated circuit is configured to receive second optical signal according to oblique angle. Photonic integrated circuit is configured to couple first optical signal to fiber according to oblique angle.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 26, 2023
    Inventors: Sheng-Fu LIN, Po-Kuan SHEN, Chun-Chiang YEN, Yi-Ting LU, Jun-Rong CHEN, Jenq-Yang CHANG, Mao-Jen WU
  • Publication number: 20230317452
    Abstract: A hard mask structure includes a tungsten-based conductive layer, a carbon-based hard mask layer and a nitride layer. The carbon-based hard mask layer is formed over the Tungsten-based conductive layer. The nitride layer is formed between the tungsten-based conductive layer and the carbon-based hard mask layer to enhance adhesion therebetween.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Sheng-Fu HUANG, Kuan Hua CHEN
  • Patent number: 11754749
    Abstract: An atmospheric turbulence detection method includes: providing a temperature difference measuring device including a thermocouple element and two sensing probes, wherein the thermocouple element has two opposite end portions, the two sensing probes are respectively disposed at the two end portions, and there is an ambient distance between the two end portions; placing the temperature difference measuring device in an atmospheric environment to generate an electromotive force by a temperature difference between the two end portions; analyzing the electromotive force to convert the electromotive force into an ambient temperature difference of an environment where the two end portions of the thermocouple element are located, an atmospheric refractive index structure constant is calculated according to the ambient temperature difference and the ambient distance, and a value of the atmospheric refractive index structure constant corresponds to an ambient disturbance of an atmospheric turbulence.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 12, 2023
    Assignee: National Central University
    Inventors: Sheng-Hsiang Wang, Kun-Hsu Wu, Sheng-Fu Hu
  • Patent number: 11742242
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: August 29, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Sheng-Fu Huang
  • Patent number: 11715734
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Patent number: D1018907
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 19, 2024
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin