Patents by Inventor Sheng-Fu Huang
Sheng-Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047395Abstract: A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.Type: ApplicationFiled: August 8, 2022Publication date: February 8, 2024Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
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Publication number: 20230361021Abstract: A semiconductor interconnection structure includes a lower inter-level dielectric layer located above a substrate, a lower metal via located in the lower inter-level dielectric layer, a first horizontal dielectric layer located over the lower inter-level dielectric layer and the lower metal via, an upper inter-level dielectric layer located over the first horizontal dielectric layer and having a dielectric constant smaller than that of the first horizontal dielectric layer, an upper metal via located in the upper inter-level dielectric layer and the first horizontal dielectric layer, and electrically connected to the lower metal via, a diffusion barrier layer located around the upper metal via, and located between the upper inter-level dielectric layer and the upper metal via; and a dielectric sidewall located the diffusion barrier layer and the upper inter-level dielectric layer.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Inventor: Sheng-Fu HUANG
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Publication number: 20230317452Abstract: A hard mask structure includes a tungsten-based conductive layer, a carbon-based hard mask layer and a nitride layer. The carbon-based hard mask layer is formed over the Tungsten-based conductive layer. The nitride layer is formed between the tungsten-based conductive layer and the carbon-based hard mask layer to enhance adhesion therebetween.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Sheng-Fu HUANG, Kuan Hua CHEN
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Patent number: 11742242Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.Type: GrantFiled: January 26, 2022Date of Patent: August 29, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Shing-Yih Shih, Sheng-Fu Huang
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Patent number: 11610996Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: GrantFiled: March 22, 2021Date of Patent: March 21, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Patent number: 11387207Abstract: A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer.Type: GrantFiled: November 13, 2020Date of Patent: July 12, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Sheng-Fu Huang
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Patent number: 11383195Abstract: A device for capturing particles includes a gas-guiding unit, a gas-guiding unit and a mist-elimination unit. The gas-guiding unit has opposing first and second ends. The mist-elimination unit is disposed at the second end. The liquid-circulation unit, disposed under the mist-elimination unit by surrounding the gas-guiding unit, includes through holes below the gas-guiding unit by a gap. A gas containing particles enters the channel via the first end and then the mist-elimination unit via the second end. While the gas flows into the channel, the liquid in the liquid-circulation unit is inhaled into the channel via the gap to form droplets containing particles. After the droplets are captured by the mist-elimination unit, the liquid formed at the mist-elimination unit flows down into the liquid-circulation unit to reform the liquid to be further inhaled back to the channel of the gas-guiding unit via the gap.Type: GrantFiled: June 18, 2020Date of Patent: July 12, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Jen Ho, Sheng-Fu Huang, Yen-Chun Liu, Chun-Yi Chou
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Publication number: 20220157761Abstract: A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventor: Sheng-Fu HUANG
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Publication number: 20220148915Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Shing-Yih Shih, Sheng-Fu Huang
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Patent number: 11289370Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.Type: GrantFiled: March 2, 2020Date of Patent: March 29, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Shing-Yih Shih, Sheng-Fu Huang
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Publication number: 20220005758Abstract: A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.Type: ApplicationFiled: July 1, 2020Publication date: January 6, 2022Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
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Patent number: 11217525Abstract: A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.Type: GrantFiled: July 1, 2020Date of Patent: January 4, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Shing-Yih Shih
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Publication number: 20210272844Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the TSV structure and the second dielectric layer and a part of the second substrate.Type: ApplicationFiled: March 2, 2020Publication date: September 2, 2021Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Shing-Yih Shih, Sheng-Fu Huang
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Publication number: 20210210638Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Publication number: 20210154616Abstract: A device for capturing particles includes a gas-guiding unit, a gas-guiding unit and a mist-elimination unit. The gas-guiding unit has opposing first and second ends. The mist-elimination unit is disposed at the second end. The liquid-circulation unit, disposed under the mist-elimination unit by surrounding the gas-guiding unit, includes through holes below the gas-guiding unit by a gap. A gas containing particles enters the channel via the first end and then the mist-elimination unit via the second end. While the gas flows into the channel, the liquid in the liquid-circulation unit is inhaled into the channel via the gap to form droplets containing particles. After the droplets are captured by the mist-elimination unit, the liquid formed at the mist-elimination unit flows down into the liquid-circulation unit to reform the liquid to be further inhaled back to the channel of the gas-guiding unit via the gap.Type: ApplicationFiled: June 18, 2020Publication date: May 27, 2021Inventors: TSUNG-JEN HO, SHENG-FU HUANG, YEN-CHUN LIU, CHUN-YI CHOU
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Patent number: 10991828Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: GrantFiled: March 20, 2019Date of Patent: April 27, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Publication number: 20210043545Abstract: A semiconductor device includes a first semiconductor wafer, a second semiconductor wafer, and a first conductive via. The first semiconductor wafer includes a first substrate and at least one first conductive layer disposed on a top surface of the first substrate. The second semiconductor wafer is disposed on the first semiconductor wafer. The second semiconductor wafer includes a second substrate and a first conductive pad disposed on a top surface of the second substrate. The first conductive via extends from the first conductive pad to the first conductive layer.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
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Publication number: 20200303559Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Fu Huang, Chung-Hsun Huang
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Patent number: 5020558Abstract: An automatic umbrella includes a telescopic shaft having a lower outer tube telescopically mounted with an upper inner tube, a locking device pivotally formed in a grip and a lower portion of the central shaft having a single hook portion respectively engageable with two hook holes formed in a lower runner pivotally secured with a plurality of stretcher ribs of a rib assembly of the umbrella for locking a folded umbrella by engaging a lower hook hole in the lower runner with the hook portion of the locking device and for shielding the rib tips into the grip by engaging the hook portion with an upper hook hole of the lower runner, thereby stably locking the folded umbrella.Type: GrantFiled: October 29, 1990Date of Patent: June 4, 1991Inventor: Sheng-Fu Huang
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Patent number: D1018907Type: GrantFiled: November 15, 2021Date of Patent: March 19, 2024Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin