Patents by Inventor Sheng-Han TSAI

Sheng-Han TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022825
    Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.
    Type: Application
    Filed: November 15, 2023
    Publication date: January 16, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Hong-Yu Guo, Tsung-Shu Lin, Hsin-Yu Pan
  • Publication number: 20250022763
    Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Hong-Yu Guo, Tsung-Shu Lin
  • Publication number: 20250022945
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Chung-En TSAI, Sheng-Syun WONG, Cheng-Han LEE, Chih-Yu MA, Shih-Chieh CHANG
  • Publication number: 20240387368
    Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chin-Yi Lin, Jie Chen, Sheng-Han Tsai, Yuan Sheng Chiu, Chou-Jui Hsu, Yu Kuei Yeh, Tsung-Shu Lin
  • Publication number: 20240120277
    Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Hong-Seng SHUE, Sheng-Han TSAI, Kuo-Chin CHANG, Mirng-Ji LII, Kuo-Ching HSU
  • Patent number: 11848270
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.
    Type: Grant
    Filed: May 25, 2019
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hong-Seng Shue, Sheng-Han Tsai, Kuo-Chin Chang, Mirng-Ji Lii, Kuo-Ching Hsu
  • Publication number: 20230386908
    Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.
    Type: Application
    Filed: August 12, 2022
    Publication date: November 30, 2023
    Inventors: Sheng-Han Tsai, Yuan Sheng Chiu, Chou-Jui Hsu, Tsung-Shu Lin
  • Publication number: 20230361027
    Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.
    Type: Application
    Filed: August 12, 2022
    Publication date: November 9, 2023
    Inventors: Chin-Yi Lin, Jie Chen, Sheng-Han Tsai, Yuan Sheng Chiu, Chou-Jui Hsu, Yu Kuei Yeh, Tsung-Shu Lin
  • Publication number: 20200058589
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.
    Type: Application
    Filed: May 25, 2019
    Publication date: February 20, 2020
    Inventors: Hong-Seng SHUE, Sheng-Han TSAI, Kuo-Chin CHANG, Mirng-Ji LII, Kuo-Ching HSU
  • Publication number: 20160371708
    Abstract: A computer-implemented method and a computer program product are provided for determining a user's level of interest in a content item during browsing of a plurality of content items. The method includes sequentially displaying a plurality of content items on a screen of a display device as a user interacts with a web-browser application, detecting a display time associated with each content item, wherein the display time is a duration for which the content item is displayed on the screen of the display device, and determining, for each of the plurality of content items displayed, a level of interest as a function of the display time associated with the content item.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 22, 2016
    Inventors: Po Ya Chuang, Wan Ping Ting, Sheng Han Tsai
  • Publication number: 20120235958
    Abstract: A sheet of piezoelectric material is configured in a chip card; alternating current (AC) is generated through bending the piezoelectric material back and forth, the alternating current (AC) is then rectified into direct current (DC) to energize the chip card display system to display stored information.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Applicant: INNOVISION FLEXTECH CORPORATION
    Inventors: Ming-Li CHEN, Chien-Chih LIN, Sheng-Han TSAI, Kun-Ze WU
  • Publication number: 20100053516
    Abstract: A transflective layer is inserted in between a light modulator and a specific-color reflector to allow partial transmission and partial reflection of the light transmitted through the light modulator. The specific-color reflector is arranged to reflect a light component of a designated color of the transmitted light.
    Type: Application
    Filed: December 8, 2008
    Publication date: March 4, 2010
    Applicant: INNOVISION FLEXTECH CORPORATION
    Inventors: Ming-Hung LU, Sheng-Han TSAI, Chien-Hung CHEN