Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) providing a first layout including a plurality of cells placed therein; (b) generating a second layout by performing a first set of calculations on the first layout such that cell congestions in the first layout is eliminated from the second layout; (c) generating a third layout by performing a second set of calculations on the second layout such that the total wire length of the third layout is less than that of the second layout; and (d) iterating the operations (b) and (c) until a target layout conforming a convergence criterion.

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

Abstract: A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

Abstract: A memory management method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The method includes associating physical erasing units with a data area or a spare area, configuring a plurality of logical addresses for mapping to the physical erasing units, and obtaining a garbage collection threshold based on a plurality of valid logical addresses among the logical addresses, and the physical erasing units mapping to the valid logical addresses are associated with the data area. The method further includes performing a garbage collection operation on the data area if the number of the physical erasing units associated with the data area is no less than the garbage collection threshold.

Abstract: A method and a system for data rebuilding and a memory control circuit unit thereof are provided. The method includes reading a plurality of physical-logical mapping information and a plurality of time information corresponding to the physical-logical mapping information stored in a rewritable non-volatile memory module. The method also includes sorting the plurality of physical-logical mapping information according to the plurality of time information corresponding to the physical-logical mapping information. The method further includes rebuilding a logical-physical mapping table according to the sorted plurality of physical-logical mapping information, and storing the rebuilt logical-physical mapping table into a buffer.

Abstract: A method and a system for data rebuilding and a memory control circuit unit thereof are provided. The method includes reading a plurality of physical-logical mapping information and a plurality of time information corresponding to the physical-logical mapping information stored in a rewritable non-volatile memory module. The method also includes sorting the plurality of physical-logical mapping information according to the plurality of time information corresponding to the physical-logical mapping infoiiiiation. The method further includes rebuilding a logical-physical mapping table according to the sorted plurality of physical-logical mapping information, and storing the rebuilt logical-physical mapping table into a buffer.