Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: In this disclosure, antiferroelectric capacitors having one or more interfacial layer/antiferroelectric layer/interfacial layer stacked structures are proposed. The compressive chemical pressure of the proposed structure leads to a reduction of the hysteresis and thus a high ESD and a low energy loss. A provided antiferroelectric capacitor demonstrates a record-high ESD of 94 J/cm3 and a high efficiency of 80%, along with a high maximum power density of 5×1010 W/kg. The degradation of the energy storage performance as the film thickness increases is alleviated by the above multi-stacked structure, which presents a high ESD of 80 J/cm3 and efficiency of 82% with the thickness scaled up to 48 nm. This improvement is attributed to the enhancement of breakdown strength due to the barrier effect of interfaces on electrical treeing. Furthermore, the capacitors also exhibit an excellent endurance up to 1010 operation cycles.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: A device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer and a top electrode. The first zirconium-containing oxide layer is over a substrate and having ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The first metal oxide layer has a thickness less than a thickness of the first zirconium-containing oxide layer. The top electrode is over the first zirconium-containing oxide layer.

Abstract: A device includes a substrate, a first zirconium-containing oxide layer, a first metal oxide layer and a top electrode. The first zirconium-containing oxide layer is over a substrate and having ferroelectricity or antiferroelectricity. The first metal oxide layer is in contact with the first zirconium-containing oxide layer. The first metal oxide layer has a thickness less than a thickness of the first zirconium-containing oxide layer. The top electrode is over the first zirconium-containing oxide layer.