Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

Abstract: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

Abstract: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

Abstract: A predetermined voltage is applied respectively on a first gate of a first metal-oxide semiconductor (MOS) transistor with a known channel length and a second gate of a second MOS transistor with an unknown channel length. A first inverse gate leakage current of the first MOS transistor and a second inverse gate leakage current of the second MOS transistor are then measured. By using the first and second inverse gate leakage currents, the channel widths of the first and the second gates, the channel length of the first gate and an equation, the channel length of the second gate is obtained.

Abstract: A predetermined voltage is applied respectively on a first gate of a first metal-oxide semiconductor (MOS) transistor with a known channel length and a second gate of a second MOS transistor with an unknown channel length. A first inverse gate leakage current of the first MOS transistor and a second inverse gate leakage current of the second MOS transistor are then measured. By using the first and second inverse gate leakage currents, the channel widths of the first and the second gates, the channel length of the first gate and an equation, the channel length of the second gate is obtained.

Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: The present invention provides a method of manufacturing a transistor with a footed offset spacer is disclosed. The method comprises providing a substrate. The gate structure is formed on the substrate and an insulating layer is then formed on the substrate and the gate structure. A portion of said insulating layer is removed by a method of anisotropic dry etching to form the footed offset spacer at a side-wall of the gate structure, wherein the footed offset spacer is formed by adjusting a first flow rate of a first gas and a second flow rate of a second flow gas in the anisotropic dry etching. The footed offset spacer can improve time delay of the propagation and power dissipation.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: A method of fabricating a shallow trench isolation is disclosed. First, a pad oxide layer and a polysilicon layer are formed on a silicon substrate. The pad oxide layer and the polysilicon layer are etched to expose parts of the substrate. Then the exposed parts of the substrate are oxidized to form an oxide layer. Next, the oxide layer is etched back to form an oxide spacer on the side wall of the polysilicon. Then, a shallow trench is formed by etching the partly exposed substrate. Next, a dielectric layer is formed to fill the shallow trench and then etched back by CMP to stop on the polysilicon layer. Finally, the pad oxide layer and the polysilicon layer are removed. As a result, oxide spacers on the side wall of the shallow trench are formed to eliminate the kink-effect.

Abstract: A method of fabricating kink-effect-free shallow trench isolations is presented in this invention. First, a layer of silicon oxide and a layer of polysilican are sequentially deposited on a substrate, and then shallow trenches are formed, next thermal oxidation is performed to grow a passivation oxide layer on the exposed silicon, and then, a dielectric layer is formed to fill into the shallow trench. Finally, the dielectric layer on the active area is removed by using chemical mechanical polishing and the polysilicon layer provides for the etching end point. The level of shallow trench is higher than the level of active area as soon as stop polishing, because the polysilicon layer is polished faster than dielectric layer. It provides the passivation oxide on the sidewall of shallow trench to form spacers of the active area after removing the polysilicon of active area. It can provide a perfect shallow trench after an oxidation and etching process to avoid the kink effect.