Patents by Inventor SHENG-HAUNG HUANG
SHENG-HAUNG HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11930645Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.Type: GrantFiled: March 5, 2023Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
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Publication number: 20230371277Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a plurality of doped regions located in a substrate; a first dielectric layer located on the substrate; a plurality of first contacts and second contacts located in the first dielectric layer and connected to the plurality of doped regions; a second dielectric layer located on the first dielectric layer; a memory element located in the second dielectric layer, the memory element being electrically connected to the second contact; and a plurality of conductive interconnects located in the second dielectric layer. The conductive interconnects being electrically connected to the plurality of first contacts, and a top surface of the conductive interconnects being at a same level as a top surface of the memory element. A method of fabricating a semiconductor device, and a semiconductor structure having a semiconductor device are also provided.Type: ApplicationFiled: July 11, 2023Publication date: November 16, 2023Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG
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Publication number: 20230225136Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.Type: ApplicationFiled: March 5, 2023Publication date: July 13, 2023Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG
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Patent number: 11600661Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a metal interconnect, and a magnetic tunneling junction (MTJ). The transistor region includes a gate over the substrate, and a doped region is at least partially in the substrate. The metal interconnect is over the doped region. The metal interconnect includes a metal via. The MTJ is entirely underneath the metal interconnect and between the doped region and the metal via, and a diameter of a bottom surface of the MTJ is greater than a diameter of an upper surface of the MTJ.Type: GrantFiled: June 9, 2021Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
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Publication number: 20210305317Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region., a metal interconnect, and a magnetic tunneling junction (MTJ). The transistor region includes a gate over the substrate, and a doped region is at least partially in the substrate. The metal interconnect is over the doped region. The metal interconnect includes a metal via. The MTJ is entirely underneath the metal interconnect and between the doped region and the metal via, and a diameter of a bottom surface of the MTJ is greater than a diameter of an upper surface of the MTJ.Type: ApplicationFiled: June 9, 2021Publication date: September 30, 2021Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG
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Patent number: 11037982Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate, a first doped region, and a second doped region at least partially in the substrate, and a contact plug directly over the gate, a first metal interconnect composed of copper over the transistor region, and a magnetic tunneling junction (MTJ) directly over the contact plug and under the first metal interconnect.Type: GrantFiled: December 17, 2019Date of Patent: June 15, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
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Publication number: 20200127049Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate, a first doped region, and a second doped region at least partially in the substrate, and a contact plug directly over the gate, a first metal interconnect composed of copper over the transistor region, and a magnetic tunneling junction (MTJ) directly over the contact plug and under the first metal interconnect.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG
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Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof
Patent number: 10510804Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.Type: GrantFiled: September 4, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang -
SEMICONDUCTOR STRUCTURE INTEGRATED WITH MAGNETIC TUNNELING JUNCTION AND MANUFACTURING METHOD THEREOF
Publication number: 20180374896Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.Type: ApplicationFiled: September 4, 2018Publication date: December 27, 2018Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG -
Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof
Patent number: 10068945Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.Type: GrantFiled: September 30, 2015Date of Patent: September 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang -
Patent number: 10038137Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.Type: GrantFiled: September 30, 2016Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Sheng-Haung Huang, Hung-Cho Wang, Kuei-Hung Shen, Shy-Jay Lin
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Publication number: 20180097175Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay CHUANG, Sheng-Haung HUANG, Hung-Cho WANG, Kuei-Hung SHEN, Shy-Jay LIN
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SEMICONDUCTOR STRUCTURE INTEGRATED WITH MAGNETIC TUNNELING JUNCTION AND MANUFACTURING METHOD THEREOF
Publication number: 20170092692Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: ALEXANDER KALNITSKY, HARRY-HAK-LAY CHUANG, SHENG-HAUNG HUANG, TIEN-WEI CHIANG