Patents by Inventor Sheng-Hsiang CHUANG
Sheng-Hsiang CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Patent number: 11929271Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.Type: GrantFiled: July 13, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Shou-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
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Patent number: 11842481Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: GrantFiled: August 4, 2022Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 11754989Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.Type: GrantFiled: November 16, 2020Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
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Patent number: 11651981Abstract: A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.Type: GrantFiled: August 18, 2020Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiao-Rou Liao, Sheng-Hsiang Chuang, Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20220375057Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 11430108Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: GrantFiled: November 16, 2020Date of Patent: August 30, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20220059415Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Publication number: 20220059376Abstract: A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.Type: ApplicationFiled: August 18, 2020Publication date: February 24, 2022Inventors: Becky LIAO, Sheng-Hsiang CHUANG, Cheng-Kang HU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
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Patent number: 11171065Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: October 14, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Patent number: 11152238Abstract: In an embodiment, a system includes a profiler configured to detect variations along a surface of a semiconductor stage; and a jig configured to move the profiler along an axis over the semiconductor stage.Type: GrantFiled: November 27, 2018Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sheng-Hsiang Chuang, Cheng-Hung Chen
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Patent number: 11120539Abstract: A method for scanning and analyzing a surface, the method comprising: receiving a piece of equipment with a target surface for inspection; receiving an input from a user; determining at least one scan parameter based on the user input; scanning the target surface using an optical detector in accordance with the at least one scan parameter; generating an image of the target surface; correcting the image of the target surface to remove at least one undesired feature to generate a corrected image based on the at least one scan parameter; and analyzing the corrected image to determine at least one geometric parameter of the target surface.Type: GrantFiled: November 29, 2018Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hsiang Chuang, Jiao-Rou Liao, Cheng-Kang Hu, Shou-Wen Kuo, Jiun-Rong Pai, Hsu-Shui Liu
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Publication number: 20210063984Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
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Publication number: 20210065347Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Inventors: Chien-Ko LIAO, Ya-Hsun HSUEH, Sheng-Hsiang CHUANG, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
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Patent number: 10889097Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.Type: GrantFiled: December 11, 2019Date of Patent: January 12, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
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Patent number: 10876976Abstract: The present disclosure provides an apparatus for substrate inspection, including a chamber, a movable holder in the chamber and configured to hold a substrate and transfer the substrate between a first position and a second position, a first inspector under the first position and the second position in the chamber, and configured to inspect a backside of the substrate, a lifter under the second position in the chamber, and configured to support the substrate and move the substrate from the second position to a third position, and a second inspector near the third position in the chamber and configured to inspect an edge of the substrate at the third position.Type: GrantFiled: August 30, 2018Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Bo-Han Shih, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 10872794Abstract: A system and method for inline detection of defects on a semiconductor wafer surface during a semiconductor device manufacturing process is disclosed herein. In one embodiment, a method includes: automatically transporting the wafer from a first processing station to an inspection station; scanning a wafer surface using a camera in the inspection station; generating at least one image of the wafer surface; analyzing the at least one image to detect defects on the wafer surface based on a set of predetermined criteria; if the wafer is determined to be defective, automatically transporting the wafer from the inspection station to a stocker; and if the wafer is determined to be not defective, automatically transporting the wafer to a second processing station for further processing in accordance with the semiconductor device manufacturing process.Type: GrantFiled: August 8, 2018Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Ya Hsun Hsueh
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Patent number: 10852704Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.Type: GrantFiled: July 6, 2018Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
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Patent number: 10839507Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: GrantFiled: August 21, 2018Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20200343115Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Cheng-Kang HU, Shou-Wen KUO, Sheng-Hsiang CHUANG, Jiun-Rong PAI, Hsu-Shui LIU