Abstract: A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

Abstract: A chip package includes a semiconductor substrate, an interlayer dielectric (ILD) layer, a first metal shielding layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, an inclined sidewall adjoining the first and second surfaces, and a through hole through the first and second surfaces. The ILD layer is located on the first surface of the semiconductor substrate, and a first conductive pad structure and a second conductive pad structure are disposed in the ILD layer. The first metal shielding layer is located on the ILD layer. A portion of the first metal shielding layer is located in the ILD layer and on the second conductive pad structure. The redistribution layer is located on the second surface of the semiconductor substrate, a wall surface of the through hole, and the first conductive pad structure.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.