Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A mode switching system including a first electronic device and the second electronic device is provided. The first electronic device includes a main control unit, a USB Type-C interface controller and a USB hub. The interface controller is coupled to the main control unit. The USB hub is coupled to the interface controller. The second electronic device is coupled to the interface controller of the first electronic device. The main control unit is configured to: (1) disable the USB hub in response to a mode switching instruction; (2) switch the mode of the interface controller from a first mode to a second mode; (3) command the interface controller to re-communicate with the second electronic device.

Abstract: A mode switching system including a first electronic device and the second electronic device is provided. The first electronic device includes a main control unit, a USB Type-C interface controller and a USB hub. The interface controller is coupled to the main control unit. The USB hub is coupled to the interface controller. The second electronic device is coupled to the interface controller of the first electronic device. The main control unit is configured to: (1) disable the USB hub in response to a mode switching instruction; (2) switch the mode of the interface controller from a first mode to a second mode; (3) command the interface controller to re-communicate with the second electronic device.