Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

Abstract: An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The fin has a wide portion and a width-transition portion. The width-transition portion tapers away from the wide portion in a top view of the substrate, and a first top surface of the wide portion is higher than a second top surface of the width-transition portion. The semiconductor device structure includes a gate stack wrapped around the wide portion. The semiconductor device structure includes a dielectric dummy gate wrapped around the width-transition portion.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction. The integrated circuit includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.

Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.

Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.