Abstract: A directional antenna structure is provided, which includes a patch antenna, a reflection plate, a cable connector, and a frame for the patch antenna, the reflection plate, and the cable connector to be fixed and assembled thereon. Through such a modular design, the antenna structure is manufactured and assembled through a simplified process, and besides this advantage, the antenna structure is further selectively integrated with a housing having the same assembly interface, and thus becoming a modular antenna structure integrated with various housings.

Abstract: A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.

Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Abstract: A method of reducing leakage current of a photodiode on a semiconductor wafer. The semiconductor wafer has a p-type substrate, a photosensing area, and at least one shallow trench surrounding the photosensing area. First, a doped polysilicon layer containing p-type dopants is formed in the shallow trench. Then, the p-type dopant in the doped polysilicon layer is caused to diffuse into the p-type substrate to form a p-type doped region surrounding a bottom of the shallow trench and walls of the shallow trench. After that, the doped polysilicon layer is removed and an insulator material is filled into the shallow trench to form a shallow trench isolation (STI) structure. Finally, an n-type doped region is implanted to form a photosensor. Here, the p-type doped region in the photosensing area is used to decrease the electric field surrounding the photosensing area and decrease the leakage current.

Abstract: A method of reducing leakage current of a photodiode on a semiconductor wafer. The semiconductor wafer has a p-type substrate, a photosensing area, and at least one shallow trench surrounding the photosensing area. First, a doped polysilicon layer containing p-type dopants is formed in the shallow trench. Then, the p-type dopant in the doped polysilicon layer is caused to diffuse into the p-type substrate to form a p-type doped region surrounding a bottom of the shallow trench and walls of the shallow trench. After that, the doped polysilicon layer is removed and an insulator material is filled into the shallow trench to form a shallow trench isolation (STI) structure. Finally, an n-type doped region is implanted to form a photosensor. Here, the p-type doped region in the photosensing area is used to decrease the electric field surrounding the photosensing area and decrease the leakage current.

Abstract: A P-well and an N-well adjacent to the P-well are formed within a semiconductor substrate. A silicon nitride layer having an opening and a silicon oxide layer are then formed, respectively, on the semiconductor substrate. The silicon oxide layer fills the opening in the silicon nitride layer. Following that, a chemical mechanical polishing process removes portions of the silicon oxide layer to align the surface of the remaining silicon oxide layer with the surface of the silicon nitride layer to form an insulator. Subsequently, the silicon nitride layer is completely removed followed by forming a gate layer positioned on the P-well and N-well, a side of the gate layer being positioned on the surface of the insulator. Finally, an ion implantation process is performed to form N-type doping regions on the P-well and the N-well as a source and a drain of an LD MOS transistor, completing fabrication of the LD MOS transistor.

Abstract: The present invention provides a method for integrating the fabrication of a sensor and a high voltage devices. The N conductive type sensor has a P conductive type doped region in the substrate of the sensor active region to effectively reduce the leakage at edges of the field oxide. Furthermore, there are the P conductive type field and the P conductive type well used as isolations for the sensor and these isolations can prevent blooming. Between these isolations, high voltage devices can be simultaneously formed thereon.

Abstract: A method for fabricating a high vltage device with double diffusion structure provides a pad oxide layer on a silicon substrate. A silicon nitride layer is formed and patterned to expose isolation regions. A first mask covers the partial isolation regions spaced from the silicon nitride layer. A well region is formed underlay the silicon nitride layer. A second mask covers the partial isolation region spaced from the silicon nitride layer and the partial silicon nitride layer. First doped regions are formed underlay the partial silicon nitride layer. Then the isolation regions are formed partially on the first doped regions. Next, a third mask covers the pad oxide layer and the partial isolation regions and second doped regions are formed spaced from the first doped regions and below the isolation regions. A gate is formed and located between the first doped regions and a spacer on a side-wall thereof. Third doped regions are formed in the first doped regions.

Abstract: A method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate is provided. A substrate is provided. An oxide layer is formed on the substrate. An N well is formed in the substrate. A P well is formed opposite to the N well in the substrate. A plurality of N-field regions are formed as drift regions in the P well and as isolation regions in the N well. A plurality of P-field regions are formed as drift regions in the N well and as isolation regions in the P well region. A plurality of field oxide regions are formed on the N well and the P well in the substrate. N− type doped regions are formed in the P well through an N-grade implantation, prior to a gate oxide layer and a polysilicon layer formation. An N+ type doped region in the N−type doped region is formed as a source/drain region for an NMOS transistor in the P well. A P+ type doped region is formed as a source/drain region for a PMOS transistor in the N well.

Abstract: A method for forming complementary metal-oxide semiconductor sensor is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. A first oxide layer is formed on the surface of the semiconductor substrate. A nitride layer is formed on the surface of the first oxide layer. Thus, p-type ions are first implanted into the semiconductor substrate to form a p-type well region. The p-type well region is annealed. The nitride layer is removed. The first oxide layer is removed. The second oxide layer is deposited on the surface of the semiconductor substrate. The p-type ions are secondly implanted into the second p-type well region to form a p-type field. The p-type field is annealed. The n-type ions are thirdly implanted into the semiconductor substrate as an n-type region abutting the oxide layer below. The n+-type ions are fourthly implanted into the n-type region as n+-type regions.

Abstract: A method for forming a high voltage and low voltage device is disclosed. According to the process, by the protection of the photoresist, the cap oxide layer on a high voltage device will not be removed in the dry etching process, and with the isolaton of cap oxide layer, the metal layer will not react on high voltage device to produce metal silicide. Accordingly, the high voltage device will not be spoiled by the silicide. The method tolerates normal silicide process, and high current feature of low voltage logic device. In addition, the prior cell library is still suitable for this process.

Abstract: A method for forming bipolar junction transistor with high gain via formulation of high voltage device in deep submicron process is disclosed. A substrate including a first part, a second part, and a third part is primarily provided; then, a first well in the first part and a second well in the second part are formed. A plurality of field oxide regions are formed on said substrate; subsequently, two third wells are formed in said third part. The following steps are to form a fourth well in said first well in said first part and two fifth wells in said second well in said second part; and to form a first gate on said first part between said two third wells, and a second gate on said second part between said two fifth wells. Next, a first spacer against said first gate and a second spacer against said second gate are formed. Further, first ions are introduced into said first part to serve as a collector region, and into said third part to serve as a first source/drain region.