Patents by Inventor Sheng-Hsu Liu
Sheng-Hsu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11955536Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.Type: GrantFiled: July 15, 2021Date of Patent: April 9, 2024Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
-
Publication number: 20230246090Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Shih-Hsien Huang, Sheng-Hsu Liu, Wen Yi Tan
-
Patent number: 11658229Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.Type: GrantFiled: June 29, 2020Date of Patent: May 23, 2023Inventors: Shih-Hsien Huang, Sheng-Hsu Liu, Wen Yi Tan
-
Patent number: 11637183Abstract: A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.Type: GrantFiled: February 14, 2022Date of Patent: April 25, 2023Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
-
Publication number: 20220399459Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.Type: ApplicationFiled: July 15, 2021Publication date: December 15, 2022Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, WEN YI TAN
-
Publication number: 20220165849Abstract: A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.Type: ApplicationFiled: February 14, 2022Publication date: May 26, 2022Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, WEN YI TAN
-
Patent number: 11289575Abstract: A semiconductor transistor is formed on a substrate of a first conductivity type. The substrate has a main surface. An ion well of the second conductivity type is disposed in the substrate. A source region and a drain region spaced apart from the source region are disposed within the ion well. The source region and the drain region have the first conductivity type. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate and is disposed between the source region and the drain region. A gate is disposed on the epitaxial channel layer. A gate dielectric layer is disposed between gate and the epitaxial channel layer.Type: GrantFiled: March 27, 2020Date of Patent: March 29, 2022Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
-
Publication number: 20210376125Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.Type: ApplicationFiled: June 29, 2020Publication date: December 2, 2021Inventors: Shih-Hsien Huang, Sheng-Hsu Liu, Wen Yi Tan
-
Publication number: 20210242312Abstract: A semiconductor transistor is formed on a substrate of a first conductivity type. The substrate has a main surface. An ion well of the second conductivity type is disposed in the substrate. A source region and a drain region spaced apart from the source region are disposed within the ion well. The source region and the drain region have the first conductivity type. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate and is disposed between the source region and the drain region. A gate is disposed on the epitaxial channel layer. A gate dielectric layer is disposed between gate and the epitaxial channel layer.Type: ApplicationFiled: March 27, 2020Publication date: August 5, 2021Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, WEN YI TAN
-
Patent number: 10825925Abstract: A fabricating method of a transistor structure includes providing a substrate with a doped well disposed within the substrate. Later, a gate structure is formed to be disposed on the doped well. Next, a hexagonal-shaped trench is formed to be embedded in the doped well at one side of the gate structure. Subsequently, a first epitaxial layer is formed to be disposed inside the hexagonal-shaped trench and contact the hexagonal-shaped trench, wherein the first epitaxial layer includes first type dopants. Finally, a second epitaxial layer including second-type dopants is formed to be disposed in the hexagon-shaped trench, wherein the first epitaxial layer surrounds the second epitaxial layer, the second epitaxial layer serves as a source/drain doped region of the transistor structure, and the first-type dopants and the second-type dopants are different conductive types.Type: GrantFiled: January 8, 2020Date of Patent: November 3, 2020Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
-
Publication number: 20200212216Abstract: A fabricating method of a transistor structure includes providing a substrate with a doped well disposed within the substrate. Later, a gate structure is formed to be disposed on the doped well. Next, a hexagonal-shaped trench is formed to be embedded in the doped well at one side of the gate structure. Subsequently, a first epitaxial layer is formed to be disposed inside the hexagonal-shaped trench and contact the hexagonal-shaped trench, wherein the first epitaxial layer includes first type dopants. Finally, a second epitaxial layer including second-type dopants is formed to be disposed in the hexagon-shaped trench, wherein the first epitaxial layer surrounds the second epitaxial layer, the second epitaxial layer serves as a source/drain doped region of the transistor structure, and the first-type dopants and the second-type dopants are different conductive types.Type: ApplicationFiled: January 8, 2020Publication date: July 2, 2020Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, WEN YI TAN
-
Patent number: 10573737Abstract: A transistor structure includes a substrate. A gate structure is disposed on the substrate. A hexagonal-shaped trench is disposed in the substrate at one side of the gate structure. A first epitaxial layer including first-type dopants is disposed in the hexagonal-shaped trench and contacts the hexagonal-shaped trench. A second epitaxial layer including second-type dopants is disposed in the hexagon-shaped trench. The first epitaxial layer is outside of the second epitaxial layer. The second epitaxial layer serves as a source/drain doped region of the transistor structure. The first-type dopants and the second-type dopants are of different conductive types.Type: GrantFiled: January 29, 2019Date of Patent: February 25, 2020Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
-
Patent number: 10236179Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.Type: GrantFiled: April 14, 2016Date of Patent: March 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Cheng Yen, Tsung-Mu Yang, Sheng-Hsu Liu, Tsang-Hsuan Wang, Chun-Liang Kuo, Yu-Ming Hsu, Chung-Min Tsai, Yi-Wei Chen
-
Patent number: 10158022Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.Type: GrantFiled: August 20, 2017Date of Patent: December 18, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-Wei Chen
-
Patent number: 9847393Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.Type: GrantFiled: October 5, 2016Date of Patent: December 19, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Chun-Liang Kuo, Tsang-Hsuan Wang, Sheng-Hsu Liu, Chieh-Lung Wu, Chung-Min Tsai, Yi-Wei Chen
-
Publication number: 20170345938Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.Type: ApplicationFiled: August 20, 2017Publication date: November 30, 2017Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-Wei Chen
-
Publication number: 20170338327Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate structures are disposed on a substrate. The epitaxial structure is disposed in the substrate between the gate structures, wherein a protruding portion of the substrate extends into the epitaxial structure in a protection direction.Type: ApplicationFiled: June 19, 2016Publication date: November 23, 2017Inventors: Sheng-Hsu Liu, Jhen-Cyuan Li, Shui-Yen Lu
-
Publication number: 20170301536Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.Type: ApplicationFiled: April 14, 2016Publication date: October 19, 2017Inventors: Fu-Cheng Yen, Tsung-Mu Yang, Sheng-Hsu Liu, Tsang-Hsuan Wang, Chun-Liang Kuo, Yu-Ming Hsu, Chung-Min Tsai, Yi-Wei Chen
-
Patent number: 9780218Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.Type: GrantFiled: May 2, 2016Date of Patent: October 3, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-wei Chen
-
Publication number: 20170243954Abstract: A method of forming a FinFET device includes following steps. First of all, a fin shaped structure is formed on a substrate. Then, a portion of the fin shaped structure is removed to form a first trench in the fin shaped structure. Next, a cover film is formed to partially cover surfaces of the first trench and to expose a portion of the fin shaped structure. Afterward, the exposed portion of the fin shaped structure is further removed to form a second trench under the first trench. Finally, a barrier layer is formed on surfaces of the second trench, thereby improving the current leakage issues.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Inventors: Jhen-Cyuan Li, Sheng-Hsu Liu, Shui-Yen Lu