Patents by Inventor Sheng-Hsuan Wei
Sheng-Hsuan Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11676895Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.Type: GrantFiled: July 30, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, Tai-Yang Wu
-
Patent number: 11355436Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: GrantFiled: December 28, 2020Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, TaiYang Wu
-
Publication number: 20220169956Abstract: Described herein is a non-aqueous composition including (a) an organic protic solvent, (b) ammonia, and (c) at least one additive of formulae I or II where R1 is H R2 is selected from H, C1 to C10 alkyl, C1 to C10 alkoxy, C6 to C10 aryl, and C6 to C10 aroxy, R3 is selected from R2, R4 is selected from C1 to C10 alkyl, C1 to C10 alkoxy, C6 to C10 aryl, and C6 to C10 aroxy, R10, R12 are independently selected from C1 to C10 alkyl and C1 to C10 alkoxy, m is 1, 2 or 3, and n is 0 or an integer from 1 to 100.Type: ApplicationFiled: March 27, 2020Publication date: June 2, 2022Inventors: Chi Yueh Kao, Mei Chin Shen, Sheng Hsuan Wei, Daniel Loeffler, Andreas Klipp, Marcel Brill, Szilard Csihony, Frank Pirrung, Niklas Benjamin Heine
-
Patent number: 11180719Abstract: The invention relates to the use of a non-aqueous composition comprising an organic solvent and at least one particular siloxane-type additive for treating substrates comprising patterns having line-space dimensions of 50 nm or below and aspect ratios of 4 or more as well as a method for manufacturing integrated circuit devices, optical devices, micromachines and mechanical precision devices, the said method comprising the steps of (1) providing a substrate having patterned material layers having line-space dimensions of 50 nm, aspect ratios of greater or equal 4, or a combination thereof, (2) contacting the substrate at least once with a non-aqueous composition, and (3) removing the non-aqueous composition from the contact with the substrate, wherein the non-aqueous composition comprising an organic solvent and at least one of such siloxane-type additives.Type: GrantFiled: October 29, 2018Date of Patent: November 23, 2021Assignee: BASF SEInventors: Daniel Loeffler, Mei Chin Shen, Sheng Hsuan Wei, Frank Pirrung, Lothar Engelbrecht, Yeni Burk, Andreas Klipp, Marcel Brill, Szilard Csihony
-
Publication number: 20210358841Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, Tai-Yang WU
-
Patent number: 11081445Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.Type: GrantFiled: July 22, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, Tai-Yang Wu
-
Publication number: 20210143101Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: ApplicationFiled: December 28, 2020Publication date: May 13, 2021Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
-
Patent number: 10879179Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: GrantFiled: December 18, 2018Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, TaiYang Wu
-
Publication number: 20200255772Abstract: The invention relates to the use of a non-aqueous composition comprising an organic solvent and at least one particular siloxane-type additive for treating substrates comprising patterns having line-space dimensions of 50 nm or below and aspect ratios of 4 or more as well as a method for manufacturing integrated circuit devices, optical devices, micromachines and mechanical precision devices, the said method comprising the steps of (1) providing a substrate having patterned material layers having line-space dimensions of 50 nm, aspect ratios of greater or equal 4, or a combination thereof, (2) contacting the substrate at least once with a non-aqueous composition, and (3) removing the non-aqueous composition from the contact with the substrate, wherein the non-aqueous composition comprising an organic solvent and at least one of such siloxane-type additives.Type: ApplicationFiled: October 29, 2018Publication date: August 13, 2020Applicant: BASF SEInventors: Daniel LOEFFLER, Mei Chin SHEN, Sheng Hsuan WEI, Frank PIRRUNG, Lothar ENGELBRECHT, Yeni BURK, Andreas KLIPP, Marcel BRILL, Szilard CSIHONY
-
Publication number: 20190348362Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.Type: ApplicationFiled: July 22, 2019Publication date: November 14, 2019Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, Tai-Yang WU
-
Publication number: 20190157204Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: ApplicationFiled: December 18, 2018Publication date: May 23, 2019Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
-
Patent number: 10157843Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: GrantFiled: November 17, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, TaiYang Wu
-
Publication number: 20180076141Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: ApplicationFiled: November 17, 2017Publication date: March 15, 2018Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
-
Patent number: 9881870Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.Type: GrantFiled: June 9, 2016Date of Patent: January 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Pei-Ru Lee, Tai-Yang Wu
-
Patent number: 9852992Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: GrantFiled: April 11, 2017Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Li-Yu Lee, TaiYang Wu
-
Publication number: 20170221827Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: ApplicationFiled: April 11, 2017Publication date: August 3, 2017Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, TaiYang WU
-
Publication number: 20170194243Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.Type: ApplicationFiled: June 9, 2016Publication date: July 6, 2017Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Pei-Ru LEE, Tai-Yang WU
-
Patent number: 9653348Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.Type: GrantFiled: May 17, 2016Date of Patent: May 16, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheng-Hsuan Wei, Pei-Ru Lee, Tai-Yang Wu