Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: A management technology for mapping data of a non-volatile memory is shown. A controller establishes a first mapping table and a second mapping table. By looking up the first mapping table, the controller maps a first logical address issued by the host for data reading to a first block substitute. By looking up the second mapping table, the controller maps the first block substitute to a first physical block of the non-volatile memory. The first mapping table further records a first offset for the first logical address. According to the first offset recorded in the first mapping table, the first logical address is mapped to a first data management unit having the first offset in the first physical block represented by the first block substitute.

Abstract: A management technology for mapping data of a non-volatile memory is shown. A controller establishes a first mapping table and a second mapping table. By looking up the first mapping table, the controller maps a first logical address issued by the host for data reading to a first block substitute. By looking up the second mapping table, the controller maps the first block substitute to a first physical block of the non-volatile memory. The first mapping table further records a first offset for the first logical address. According to the first offset recorded in the first mapping table, the first logical address is mapped to a first data management unit having the first offset in the first physical block represented by the first block substitute.

Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.

Abstract: The invention introduces a method for controlling data access to a flash memory, performed by a processing unit, including steps of: obtaining a logical address associated with a data read operation; determining whether a group table corresponding to the logical address is queued in a locked queue, or a hot zone of a swap queue; and prohibiting content of the locked queue and the swap queue from being modified when the group table corresponding to the logical address is queued in the locked queue, or the hot zone of the swap queue.

Abstract: The invention introduces a method for controlling data access to a flash memory, performed by a processing unit, including steps of: obtaining a logical address associated with a data read operation; determining whether a group table corresponding to the logical address is queued in a locked queue, or a hot zone of a swap queue; and prohibiting content of the locked queue and the swap queue from being modified when the group table corresponding to the logical address is queued in the locked queue, or the hot zone of the swap queue.

Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.

Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a controller. The flash memory stores a logical-to-physical mapping (L2P) table which is divided into a plurality of group-mapping tables. The DRAM stores a first set of the group-mapping tables. The controller loads a second set of the group mapping tables from the flash memory to the DRAM to replace the first set of the group-mapping tables using a predetermined replacement mechanism, and each group-mapping table of the second set has a corresponding column in an access information table that includes a flag and an access count. In response to the corresponding column of a specific group-mapping table in the second set not being zero, the controller excludes the specific group-mapping table from the predetermined replacement mechanism.

Abstract: A data storage device is provided. The data storage device includes: a flash memory and a microcontroller. The flash memory includes a plurality of physical blocks. The microcontroller selects one source block and one destination block from the plurality of physical blocks, and performs a garbage collection operation according to a check map corresponding to the selected source block to copy data stored in one or more valid physical addresses of the source block to the selected destination block.

Abstract: A data storage device is provided. The data storage device includes: a flash memory and a microcontroller. The flash memory includes a plurality of physical blocks. The microcontroller selects one source block and one destination block from the plurality of physical blocks, and performs a garbage collection operation according to a check map corresponding to the selected source block to copy data stored in one or more valid physical addresses of the source block to the selected destination block.

Abstract: The present invention relates to a transmission interface device capable of calibrating the transmission frequency automatically, which comprises a clock generating unit, a data transmission unit, and a control unit. The clock generating unit is used for generating an operating clock, which determines a transmission frequency. The data transmission unit is used for connecting to a host and transmitting a plurality of data to the host or receiving the plurality of data from the host according to the operating clock. When the host or the data transmission unit detects transmission errors in the plurality of data, the host or the data transmission unit generates an error handling. The control unit generates an adjusting signal according to the error handling and transmits the adjusting signal to the clock generating unit for adjusting the transmission frequency of the operating clock.

Abstract: A method for preparing a flame retardant modified acrylonitrile-based copolymer, includes: prepolymerizing a first composition to obtain a first prepolymer solution including a first prepolymer; prepolymerizing a second composition to obtain a second prepolymer solution including a second prepolymer; and mixing the first and second prepolymer solutions and subjecting a mixture of the first and second prepolymers to polymerization to obtain a flame retardant modified acrylonitrile-based copolymer solution containing a flame retardant modified acrylonitrile-based copolymer.

Abstract: A method for preparing a flame retardant modified acrylonitrile-based copolymer, includes: prepolymerizing a first composition to obtain a first prepolymer solution including a first prepolymer; prepolymerizing a second composition to obtain a second prepolymer solution including a second prepolymer; and mixing the first and second prepolymer solutions and subjecting a mixture of the first and second prepolymers to polymerization to obtain a flame retardant modified acrylonitrile-based copolymer solution containing a flame retardant modified acrylonitrile-based copolymer.

Abstract: The present invention relates to a transmission interface device capable of calibrating the transmission frequency automatically, which comprises a clock generating unit, a data transmission unit, and a control unit. The clock generating unit is used for generating an operating clock, which determines a transmission frequency. The data transmission unit is used for connecting to a host and transmitting a plurality of data to the host or receiving the plurality of data from the host according to the operating clock. When the host or the data transmission unit detects transmission errors in the plurality of data, the host or the data transmission unit generates an error handling. The control unit generates an adjusting signal according to the error handling and transmits the adjusting signal to the clock generating unit for adjusting the transmission frequency of the operating clock.