Abstract: The present invention discloses a concrete test device and method based on a load-corrosion coupling action, relating to the technical field of corrosion experimental devices for concrete sewage pipelines. The device simulates a real environment of a sewage pipeline based on the load-corrosion coupling action, applies mechanical load and chemical corrosion effects to a concrete specimen simultaneously, and accelerates a corrosion effect on the concrete specimen by exposing the concrete specimen. According to the device, researches on mechanical properties of a concrete material under the load-corrosion coupling action are realized, and an assessment sample basis is provided for researches on aging characteristics of the concrete sewage pipelines. The present invention further discloses a concrete test method based on the aforementioned test device.

Abstract: The present invention discloses a concrete test device and method based on a load-corrosion coupling action, relating to the technical field of corrosion experimental devices for concrete sewage pipelines. The device simulates a real environment of a sewage pipeline based on the load-corrosion coupling action, applies mechanical load and chemical corrosion effects to a concrete specimen simultaneously, and accelerates a corrosion effect on the concrete specimen by exposing the concrete specimen. According to the device, researches on mechanical properties of a concrete material under the load-corrosion coupling action are realized, and an assessment sample basis is provided for researches on aging characteristics of the concrete sewage pipelines. The present invention further discloses a concrete test method based on the aforementioned test device.

Abstract: A semiconductor device includes a substrate. A gate structure is over the substrate. Source/drain epitaxial structures are on opposite sides of the gate structure. An interlayer dielectric (ILD) structure surrounds and covers the gate structure. A dielectric liner lines a sidewall of the ILD structure and wraps a top corner of the gate structure. The dielectric liner comprises a bottom portion, a top portion above the bottom portion, and a middle portion connecting the bottom portion and the top portion, wherein the middle portion has a different composition than the bottom portion and the top portion.

Abstract: A package includes a redistribution structure that includes conductive features and first waveguides; first dies and second dies attached to the redistribution structure, wherein the first dies are different than the second dies, wherein the first dies are electrically connected to respectively corresponding second dies through the redistribution structure; and optical bridge structures attached to the redistribution structure, wherein the optical bridge structures are optically coupled to the first waveguides, wherein the optical bridge structures are electrically connected to respectively corresponding first dies and respectively corresponding second dies through the redistribution structure.

Abstract: A touch display device is provided. The touch display device includes a touch display panel and a driver circuit. The touch display panel includes a control transistor coupled to a common electrode through a liquid crystal capacitor. The driver circuit is coupled to the touch display panel, and outputs a first driving signal to a first terminal of the control transistor. When the touch display panel switches from a first operational cycle to a first transition interval, the driver circuit adjusts the first driving signal to change a voltage of the first terminal of the transistor from a first voltage to a second voltage different from the first voltage to adjust a voltage of the common electrode.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a semiconductor device including a metal-insulator-metal capacitor. The metal-insulator-metal capacitor includes a dielectric pad layer having a portion between a capacitor bottom metal electrode layer and a portion of an insulator layer. The dielectric pad layer may preserve a thickness of the insulator layer to reduce a likelihood of a leakage between a capacitor top metal electrode layer and the capacitor bottom metal electrode layer. The dielectric pad layer may also enable a reduction in a thickness of the insulator layer to increase a capacitance of the metal-insulator-metal capacitor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first electrode over a semiconductor substrate. A data storage element is on the first electrode. A second electrode is over the data storage element. A first spacer layer is on a sidewall of the second electrode. A conductive structure is over the second electrode. The conductive structure includes a first segment adjacent to the sidewall of the second electrode. The first segment extends from an upper surface of the first spacer layer to a first sidewall of the first spacer layer.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Abstract: A method of forming a package assembly includes the following operations. At least one integrated circuit structure is bonded to an interposer structure. A photonic structure is bonded to the interposer structure aside the at least one integrated circuit structure. A glass substrate is assembled to a fiber array unit. The glass substrate with the fiber array unit is bonded to the photonic structure. A laser writing process is performed to the glass substrate, so as to form a laser written waveguide structure inside the glass substrate, wherein the laser written waveguide structure is optically coupled to the fiber array unit and the photonic structure.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure comprising a waveguide. The waveguide has an input region and an output region. The input region is configured to receive light. The waveguide comprises a lower doped structure comprising a first doping type and a plurality of doped pillar structures disposed within the lower doped structure. The doped pillar structures comprise a second doping type opposite the first doping type. The doped pillar structures extend from a top surface of the lower doped structure to a point below the top surface of the lower doped structure.

Abstract: The present disclosure relates to medical implant components comprising a biocompatible-bioactive composite material layer (BACL), methods of making the medical implant components and applications of the medical implant components.

Abstract: Optical devices and methods of manufacture are presented in which interposers are incorporated with optical devices. In some embodiments a method includes embedding first optical packages within the interposers in order to provide optical bridging between different semiconductor devices. The first optical packages may be embedded with a glass core or metallization layers.

Abstract: A high-power resistor and a fabrication method thereof are provided. The method includes: providing a resistance substrate including resistance alloy material and a copper metal layer; forming a cuprous oxide layer on the resistance substrate by using the copper metal layer; sticking the resistance substrate to a ceramic substrate, in which the cuprous oxide layer is located between the resistance substrate and the ceramic substrate; performing a sintering process on the resistance substrate and the ceramic substrate to form a composite substrate; forming a plurality of terminal electrodes on the composite substrate to form the high-power resistor. Therefore, the high-power resistor includes the composite substrate and the terminal electrodes. The composite substrate includes a bonding layer disposed between the ceramic substrate and the resistance substrate to bond the resistance alloy material on the ceramic substrate, in which the bonding layer includes sintered cuprous oxide.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.