Abstract: A reliability determination method, which is configured to test a batch of semiconductor devices, includes: obtaining a Welbull distribution of lifetime of the batch of semiconductor devices; dividing the Welbull distribution into at least a first section and a second section, wherein the first section and the second section meet a confidence interval; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, in which the first trend line has a first slope and the second trend line has a second slope; determining the first slope exceeds a second slope; and determining a predicted reliability of the batch of the semiconductor device under a target quality level according to the first section.

Abstract: A reliability determination method, which is configured to test a batch of semiconductor devices, includes: obtaining a Welbull distribution of lifetime of the batch of semiconductor devices; dividing the Welbull distribution into at least a first section and a second section, wherein the first section and the second section meet a confidence interval; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, in which the first trend line has a first slope and the second trend line has a second slope; determining the first slope exceeds a second slope; and determining a predicted reliability of the batch of the semiconductor device under a target quality level according to the first section.

Abstract: A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Abstract: A semiconductor device and a method for forming the same provides a double layer contact etch stop layer selectively formed over PMOS transistors with only a single silicon nitride contact etch stop layer formed over NMOS transistors on the same chip. The composite contact etch stop layer structure formed over the PMOS transistor avoids data retention and plasma induced damage issue associated with the PMOS transistor and a single silicon nitride contact etch stop layer formed over NMOS transistors avoids device shifting issues.

Abstract: An automatically adjustable wafer probe card for the testing of integrated circuits fabricated on a wafer. The wafer probe card includes a pitch shift assembly having a shift block that includes a reserve needle block and an adjacent functional needle block. Multiple probe needles are linearly adjustable on the shift block, and a selected number of the probe needles can be shifted from the reserve needle block to the functional needle block depending on the number of contact pads on the integrated circuit to be contacted by the probe needles of the wafer probe card during the testing process. A selected spacing between the probe needles, or pitch, can be achieved by locating the probe needles at the selected spacings from each other along the functional needle block.

Abstract: An automatically adjustable wafer probe card for the testing of integrated circuits fabricated on a wafer. The wafer probe card includes a pitch shift assembly having a shift block that includes a reserve needle block and an adjacent functional needle block. Multiple probe needles are linearly adjustable on the shift block, and a selected number of the probe needles can be shifted from the reserve needle block to the functional needle block depending on the number of contact pads on the integrated circuit to be contacted by the probe needles of the wafer probe card during the testing process. A selected spacing between the probe needles, or pitch, can be achieved by locating the probe needles at the selected spacings from each other along the functional needle block.