Abstract: Cancer-targeting peptides having a PX1LX2 motif, in which X1 is His or an amino acid residue with a hydrophobic side chain and X2 is Pro, Phe, or Trp. Also disclosed herein are conjugates containing the cancer-targeting peptides and uses thereof in cancer treatment and diagnosis.

Abstract: A gas filling apparatus for filling a gas into a storage apparatus for storing a semiconductor element or a reticle is provided. The gas filling apparatus is connected with an air feed source, which includes a base, a first inlet port and a set of air feed source route. The storage apparatus is loaded on the base, and the first inlet port which is disposed on the base corresponds with the second inlet port of the storage apparatus. The set of air feed source route includes an entrance part, a supply part and a branch part. The entrance part is connected with the air feed source, and the supply part is connected with the first inlet port. The branch part is a closed loop, which transmits the gas from the entrance part into the supply part.

Abstract: This invention is about a gas filling apparatus for filling a gas into a storage apparatus for storing a semiconductor element or a reticle. The gas filling apparatus comprises a base and a port. The storage apparatus is loaded on the base. The port comprises a receiving part, which is connected with an air entrance of the storage apparatus. The contact portions of both the top of the receiving part and the air entrance of the storage apparatus are cambered surfaces and these two portions contacts in a ring fashion which is formed by the cambered surfaces mated with each other. The port also comprises a hole for the gas to pass through, and a joint port to connect with the air source.

Abstract: A method of fabricating an electronic apparatus having an active region and a peripheral region surrounding the active region is described. A first main device and a second main device are provided. An optical clear liquid adhesive (OCLA) is applied between the first main device and the second main device and within the active region. A photo-mask having a transparent region and an opaque region is provided above the second main device, and the transparent region corresponds to the peripheral region. An OCLA diffusion process is performed such that the OCLA diffuses from the active region to the peripheral region. During the OCLA diffusion process, a first irradiating process with the photo-mask is performed, such that the OCLA diffusing to the peripheral region is partially cured. After removing the photo-mask, a second irradiating process is performed, such that the OCLA is completely cured.

Abstract: A reticle POD, comprising a top cover, a bottom cover, and a plurality of supporting components deployed in the four corners of the bottom cover, the supporting component comprising: a base body perpendicularly assembled, on two sides of which being disposed with mounting blocks; a pair of elastic elements respectively placed on the base body; a pair of leading elements connecting respectively to the horizontal extension of the elastic elements and then extending lengthwise to form a tip, a first bevel and a second bevel being formed on the side of the tip located on the inner side of the base body; a supporting base plate, the first and the second ends of which being connected to the second bevel of the leading element and a supporting pillar being disposed on the third end of the supporting base plate.

Abstract: A wireless communications device is provided with a plurality of card slots, a first wireless communications module, and a second wireless communications module. The card slots are inserted with at least one subscriber identity card. The first wireless communications module performs wireless transceiving in compliance with at least a first wireless technology. The second wireless communications module determines at least a first subscriber number and a second subscriber number from the at least one subscriber identity card, and enables the wireless transceiving of the first wireless communications module using the first subscriber number. Also, the second wireless communications module performs wireless transceiving in compliance with at least a second wireless technology using the second subscriber number.

Abstract: A reticle POD, comprising a top cover, a bottom cover, and a plurality of supporting components deployed in the four corners of the bottom cover, the supporting component comprising: a base body perpendicularly assembled, on two sides of which being disposed with mounting blocks; a pair of elastic elements respectively placed on the base body; a pair of leading elements connecting respectively to the horizontal extension of the elastic elements and then extending lengthwise to form a tip, a first bevel and a second bevel being formed on the side of the tip located on the inner side of the base body; a supporting base plate, the first and the second ends of which being connected to the second bevel of the leading element and a supporting pillar being disposed on the third end of the supporting base plate.

Abstract: A graphics card includes a graphics processing unit (GPU), a heat dissipation fin, an electric cooling module and a thermoelectric generator. The electric cooling module has a cold side and a hot side. The cold side contacts the GPU, and the hot side contacts the heat dissipation fin. The thermoelectric generator contacts the heat dissipation fin and is electrically connected to the electric cooling module. Furthermore, a method for dissipating the heat of the graphics card is also disclosed herein.

Abstract: An instant image processing system comprises a graphic processing module and a format transforming module. The graphic processing module is used to receive a video signal and execute a digital image processing program on the video signal to generate processed video data. In response to a remote display demand, the format transforming module transforms the processed video data to transformed video data with a network transmission format.

Abstract: A graphics card includes a graphics processing unit (GPU), a heat dissipation fin, an electric cooling module and a thermoelectric generator. The electric cooling module has a cold side and a hot side. The cold side contacts the GPU, and the hot side contacts the heat dissipation fin. The thermoelectric generator contacts the heat dissipation fin and is electrically connected to the electric cooling module. Furthermore, a method for dissipating the heat of the graphics card is also disclosed herein.

Abstract: This invention is about a gas filling apparatus for filling a gas into a storage apparatus for storing a semiconductor element or a reticle. The gas filling apparatus comprises a base and a port. The storage apparatus is loaded on the base. The port comprises a receiving part, which is connected with an air entrance of the storage apparatus. The contact portions of both the top of the receiving part and the air entrance of the storage apparatus are cambered surfaces and these two portions contacts in a ring fashion. The port also comprises a hole for the gas to pass through, and a joint port to connect with the air source.

Abstract: This present invention provides a gas filling apparatus for filling a gas into a storage apparatus for storing a semiconductor element or a reticle. The gas filling apparatus is connected with an air feed source, and includes a base, a first inlet port and a set of air feed source route. The storage apparatus is loaded on the base, and the first inlet port which is disposed on the base corresponds with the second inlet port of the storage apparatus. The set of air feed source route includes an entrance part, a supply part and a branch part. The entrance part is connected with the air feed source, and the supply part is connected with the first inlet port. The branch part is a closed loop, which transmits the gas from the entrance part into the supply part.

Abstract: The present invention provides a storage apparatus for storing a semiconductor element or a reticle and having a filter therein. The storage apparatus includes a first cover and a second cover, which are assembled together to form an inner space therebetween for accommodating a reticle or a semiconductor element. The second cover of the storage apparatus is composed of a body and a plate. Further, the second cover includes at least one aperture for communicating the inner space and an outer of the storage apparatus. The plate has a corresponding portion positionally corresponding to the aperture of the body. The filter is sandwiched between the body and the plate and covered the aperture so that when the air passes through the aperture of the body, the filter can filter and rid the air of impurities.

Abstract: The present invention provides a storage apparatus, ex. reticle pod, FOUP, FOSB or any kind of wafer pod, for storing a semiconductor element, ex. wafer, or a reticle and having a filter module therein. The storage apparatus is composed of a first cover and a second cover, which are assembled together to form an inner space therebetween for accommodating a reticle or a semiconductor element. The second cover of the storage apparatus comprises at least one aperture for communicating the inner space and an exterior of the storage apparatus and a filter module for covering the aperture.

Abstract: An I/O shield used in an electronic apparatus is provided. The electronic apparatus comprises a casing having an opening. The I/O shield comprises a body and at least a flexible lateral plate. The body has an edge with many protrusions arranged thereon. The flexible lateral plate has a first lateral edge and a second lateral edge parallel to the first lateral edge. The first lateral edge is disposed on the edge. The flexible lateral plate tilts towards the protrusions, and a surface of the flexible lateral plate faces the protrusions. When a rim of the opening is situated between the protrusions and the flexible lateral plate, the flexible lateral plate forms a bend structure between the first lateral edge and the second lateral edge, so that part of the surface near the second lateral edge presses the rim and clamps the rim of the opening together with the protrusions.

Abstract: In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals.

Abstract: A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals.

Abstract: In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals.

Abstract: In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals.

Abstract: In one embodiment of the present invention, an oscillator activator includes a trigger circuit, a controller, and a stability generator. The trigger circuit generates a trigger signal based on a reset signal. The controller controls generation of an oscillator signal from a main oscillator based on the reset signal. The stability generator generates a stability indicator signal in response to the trigger signal. The stability indicator signal indicates a stable condition of the main oscillator corresponding to a start-up time of the main oscillator.