Abstract: A method includes: depositing a mask layer over a substrate; directing first radiation reflected from a central collector section of a sectional collector of a lithography system toward the mask layer according to a pattern; directing second radiation reflected from a peripheral collector section of the sectional collector toward the mask layer according to the pattern, wherein the peripheral collector section is vertically separated from the central collector section by a gap; forming openings in the mask layer by removing first regions of the mask layer exposed to the first radiation and second regions of the mask layer exposed to the second radiation; and removing material of a layer underlying the mask layer exposed by the openings.

Abstract: A system for a semiconductor fabrication facility includes a maintenance tool, a control unit, a first track, a second track, a maintenance crane movably mounted on the first track, a plurality of first sensors disposed on the first track, an OHT vehicle movably mounted on the second track, and a second sensor on the OHT vehicle. The first sensors detect a location of the maintenance crane and generate a first location data to the control unit. The second sensor generates a second location data to the control unit.

Abstract: A method for inspecting an extreme ultraviolet (EUV) light source includes: removing a collector mirror of the EUV light source from a collector chamber; installing an inspection apparatus within the collector chamber, the apparatus including a selectively extendable and retractable member and a camera at one end of the member; operating a first actuator to extend the member along a path through the interior chamber of the EUV light source, thereby moving the camera to a given position within the interior chamber of the EUV light source; operating a second actuator to pan the camera about an axis of rotation, thereby establishing a given camera orientation within the interior of the EUV light source; and, capturing an image of the interior chamber of the EUV light source with the camera while the camera is at the given position and orientation established by the operation of the first and second actuators.

Abstract: A method for using an extreme ultraviolet radiation source is provided. The method includes assembling a first droplet generator onto a port of a vessel; ejecting a target droplet from the first droplet generator to a zone of excitation in front of a collector; emitting a laser toward the zone of excitation, such that the target droplet is heated by the laser to generate extreme ultraviolet (EUV) radiation; stopping the ejection of the target droplet; after stopping the ejection of the target droplet, disassembling the first droplet generator from the port of the vessel; after disassembling the first droplet generator from the port of the vessel, inserting a cleaning device into the vessel through the port; and cleaning the collector by using the cleaning device.

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a collector and a plurality of vibration sensors coupled to the collector. The vibration sensors generate sensor signals indicative of shockwaves from laser pulses and impacts from debris. The system utilizes the sensor signals to improve the quality of EUV light generation.

Abstract: A system for a semiconductor fabrication facility includes a manufacturing tool including a load port, a maintenance crane, a rectangular zone overlapping with the load port of the manufacturing tool, a plurality of first sensors at corners of the rectangular zone, an OHT vehicle, a second sensor on the OHT vehicle, a third sensor on the load port, and a control unit. The first sensors are configured to detect a location of the maintenance crane and to generate a first location data. The second sensor is configured to generate a second location data. The control unit is configured to receive the first location data of the maintenance crane and the second location data of the OHT vehicle. The control unit further sends signals to the second sensor and the third sensor or to cut off the signal to the second sensor.

Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottosource/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Abstract: An approach to forming a semiconductor structure is provided. The semiconductor structure includes two adjacent fins on a substrate. A gate stack is on each of the two adjacent fins. The semiconductor structure includes a first source/drain on a first end of each fin of the two adjacent fins and a second source/drain on a second end of each fin of the two adjacent fins. The semiconductor structure includes a switching layer on at least the first source/drain on the first end of each fin of the two adjacent fins and a top electrode on the switching layer. A metal material over the top electrode in the semiconductor structure.

Abstract: A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.

Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottom source/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Abstract: A semiconductor structure includes a first semiconducting channel having a plurality of vertical nanowires and a second semiconducting channel having a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are configured to be in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

Abstract: A semiconductor device structure for a vertical field effect transistor comprises a substrate with a shallow trench isolation (STI) region. A lower source/drain area is formed on the STI region with a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin. The third semiconductor fin is formed to couple the first semiconductor fin to the second semiconductor fin across the lower source/drain area. The STI region that is beneath the lower source/drain area comprises opposing sidewall portions curved in opposing directions. In one example the lower source/drain area is formed only at an intersection between the STI region and one or more of the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin. In other example, the second semiconductor fin is disposed parallel to the first semiconductor fin and together with the third semiconductor fin resulting in an H-shaped structure from a top-down view.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

Abstract: A method of controlling a temperature of the semiconductor device includes operating an semiconductor apparatus; maintaining a temperature of a vessel of the semiconductor apparatus with a first cooling output by a cooling controller; heating the vessel for removing a material on the vessel; transferring a first signal, by a converter, to the cooling controller when heating the vessel; and reducing the first cooling output to a second cooling output by the cooling controller base on the first signal.

Abstract: Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

Abstract: Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.