Patents by Inventor Sheng-Li Hsiao

Sheng-Li Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170084366
    Abstract: A resistor includes a body and two connecting members. The body is made from an ohmic material and has two opposite side faces. Each of the connecting members has a side surface that has a connecting region welded to a respective one of the side faces of the body.
    Type: Application
    Filed: February 29, 2016
    Publication date: March 23, 2017
    Applicant: YAGEO CORPORATION
    Inventors: Dong-Mou TSAI, Sheng-Li HSIAO, Shih-Hsin CHANG, Chih-Lung CHEN, Hwan-Wen LEE
  • Publication number: 20160360619
    Abstract: A passive device includes a substrate that has opposite first and second surfaces, an electrical connecting unit, a first passive unit, and a second passive unit. The electrical connecting unit includes a first pad formed on the first surface and a second pad formed on the second surface and is electrically connected to the first pad. The first passive unit is formed on the first surface and electrically connected to the first pad. The second passive unit is formed on the second surface and includes two separated electrode layers electrically insulated from the electrical connecting unit, and an insulator layer interconnecting the electrode layers.
    Type: Application
    Filed: November 30, 2015
    Publication date: December 8, 2016
    Applicant: YAGEO CORPORATION
    Inventors: Sheng-Li HSIAO, Yung-Han Liu, Shih-Hsin CHANG, Ping-Chuen KUO, Shu-Fang CHEN, Ching-Chang LIN
  • Patent number: 9336931
    Abstract: The disclosure provides a chip resistor including: a substrate, two first electrodes, two second electrodes, a resistive layer, at least one protection layer and at least one coating layer. The protection layer covers part of the two first electrodes, and includes at least two overlay sides and at least one overlay plane. The coating layer covers the at least two overlay sides, the at least one overlay plane, and part of the two first electrodes and the two second electrodes. The chip resistor uses the two overlay sides and the overplay plane to extend a distance between the two first electrodes and the outside. Therefore, it is difficult for the airborne sulfur, sulfides and sulfur-containing compounds to enter and react with the two first electrodes. Thus, the chip resistor can resist corrosion of harmful substances such as sulfur, sulfides and sulfur-containing compounds or halogens on the electrodes.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: May 10, 2016
    Assignee: YAGEO CORPORATION
    Inventors: Dong-Mou Tsai, Tsai-Hu Chen, Sheng-Li Hsiao, Yung-Han Liu, Jen-Fu Ho
  • Publication number: 20150357097
    Abstract: The disclosure provides a chip resistor including: a substrate, two first electrodes, two second electrodes, a resistive layer, at least one protection layer and at least one coating layer. The protection layer covers part of the two first electrodes, and includes at least two overlay sides and at least one overlay plane. The coating layer covers the at least two overlay sides, the at least one overlay plane, and part of the two first electrodes and the two second electrodes. The chip resistor uses the two overlay sides and the overplay plane to extend a distance between the two first electrodes and the outside. Therefore, it is difficult for the airborne sulfur, sulfides and sulfur-containing compounds to enter and react with the two first electrodes. Thus, the chip resistor can resist corrosion of harmful substances such as sulfur, sulfides and sulfur-containing compounds or halogens on the electrodes.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: DONG-MOU TSAI, TSAI-HU CHEN, SHENG-LI HSIAO, YUNG-HAN LIU, JEN-FU HO
  • Publication number: 20120064230
    Abstract: The steps of the present invention are as follows: (a) a detachable film is formed on both sides of a substrate, respectively; (b) a number of vias running through both sides of the detachable films are formed in the substrate; (c) the vias are filled with a conductive paste; (d) the detachable films are peeled off; (e) a metallic conductive layer is deposited on both sides of the substrate, respectively; (f) a specific mold pattern is formed on the metallic conductive layers, respectively, by a photolithographic process; (g) a metallic circuit layout layer is formed on the patterns, respectively, by an electrochemical process; and (h) the mold patterns and the metallic conductive layers are removed. As such, the substrate is not contaminated by the conductive paste. Further, by using deposition, metallic conductive layers are directly adhered to the substrate and, by using photolithography, layouts with small linewidth could be formed.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Shih-Long Wei, Sheng-Li Hsiao, Chien-Hung Ho, Hsiao-Chun Liu