Abstract: Multi-microlens arrays for optimizing light collection efficiency in CCD/CMOS solid-state color image cameras with L-shaped or non-regular photodetector areas are disclosed. Microelectronic fabrication methods for forming planar array multi-microlenses comprised of elements consisting of lens-pairs, integrated with color-filters, and compatible with CMOS high-volume manufacturing are taught. Experimental results demonstrating the processes for fabrication of multi-microlenses for L-shaped and for non-regular sensing areas are given.

Abstract: A method for alignment to an alignment mark array within a patterned electronic material layer, formed on a substrate employed in a microelectronics fabrication, with improved registration accuracy of a subsequent step-and-repeat photomask pattern. There is first provided a substrate upon which is formed a patterned microelectronics layer containing an alignment mark array. There is then formed over the substrate and patterned layer, covering over the alignment marks, a subsequent layer or layers which may be of opaque material. In order to align properly a patterned photomask for patterning the overlying layer by means of conventional photolithography, the alignment mark array is located by first scanning with a laser light source contained within a step-and-repeat apparatus containing the patterned photomask and detecting the optical radiation signal scattered from the alignment mark array.

Abstract: A method for making long focal length micro-lens for color filters in CMOS image sensor applications and device made by the method are described. In the method, a layer of micro-lens material is first spin coated on top of a color filter, patterned by a photolithographic method into at least four discrete regions, and preferably at least nine discrete regions for each micro-lens with a pre-set spacing therein between. The discrete regions allow a smaller volume of micro-lens material to be used for forming the micro-lens in a subsequent reflow process. The micro-lens formed by the present invention novel method has a focal length of at least 7 &mgr;m, and preferably at least 10 &mgr;m such that a 0.35 &mgr;m technology CMOS image sensor utilizing two or three layers of metal conductors can be formed by the present invention method.

Abstract: Within both a method for forming a patterned photoresist layer and a method for forming an electroplated patterned conductor layer while employing the patterned photoresist layer as a patterned photoresist plating mask layer there is first provided a substrate. There is then formed over the substrate a blanket photoresist layer formed of a negative photoresist material. There is then photoexposed the blanket photoresist layer to form a photoexposed blanket photoresist layer while employing a photoexposure apparatus which employs an annular edge ring exclusion apparatus positioned over an annular edge ring of the blanket photoresist layer and the substrate. Finally, there is then developed the photoexposed blanket photoresist layer to form a patterned photoresist layer having an annular edge ring excluded over the annular edge ring of the substrate.

Abstract: Formation of integrated color filters for gain-ratio balanced semiconductor array imagers using a spectrophotometric feedback control loop to adjust layer thickness during the deposition process is disclosed. The fabrication sequence of G/R/B conventionally used in Prior Art has been changed to B/R/G or B/G/R to enable the process to adapt to yielding specified color gain-ratio values without the need for integrated circuit redesign. A high efficiency color filter process is demonstrated wherein the additional neutral-density attenuator layers and/or spacer layers required in Prior Art fabrication methods are eliminated. The disclosed process is shown to enable high-precision thickness control of the color filter layers. Blue coating lift-off problems and the steric effect associated with successive depositions of color layers having step-height variations are eliminated.

Abstract: A rinse tank for rinsing electronic substrates after a chemical process and a method for utilizing such rinse tank are provided. In the rinse tank, devices for performing a quick dump rinse; for performing a cascade overflow rinse and for feeding an inert gas bubbling are provided in the cavity of a single rinse tank. By utilizing the present invention novel rinse tank, the processing problems frequently observed in conventional rinse tanks where two rinse tanks are required for the quick dump rinse and for the cascade overflow rinse, such as particle re-deposition and a large floor space area requirement are eliminated. Furthermore, the wafer rinse process after a metal etching process can be accomplished in a total process time that is at least 2˜3 minutes shorter than that required by using conventional rinse tanks.

Abstract: A process for reducing the surface roughness of a silicon dioxide gate insulator layer, that has been subjected to a boron ion implantation procedure, has been developed. The process features the use of an ammonium hydroxide-hydrogen peroxide solution, applied to the gate insulator layer, to reduce the surface roughness of the gate insulator layer, created by the boron ion implantation procedure. The treatment of the gate insulator layer, in the ammonium hydroxide-hydrogen peroxide solution, results in a surface roughness equivalent to the surface roughness of the gate insulator layer, prior to the boron ion implantation procedure.

Abstract: A microelectronic method is described for optimizing the fabrication of optical and semiconductor array structures for high efficiency color image formation in solid-state cameras. Disclosed is an ordered fabrication sequence in which microlens formation precedes color filter layer formation to enable increased image light collection efficiency, to encapsulate and protect the microlens elements from chemical and thermal processing damage, to minimize topographical underlayer variations which would axially misalign or otherwise aberrate microlens elements formed on non-planar surfaces, and, to complete the most difficult steps early in the process to minimize rework and scrap. A CMOS, CID, or CCD optoelectronic configuration is formed by photolithographically patterning a planar-array of photodiodes on a Silicon or other III-V, II-VI, or compound semiconductor substrate.

Abstract: A microelectronic method is described for optimizing the fabrication of optical and semiconductor array structures for high efficiency color image formation in solid-state cameras. Disclosed is an ordered fabrication sequence in which microlens formation precedes color filter layer formation to enable increased image light collection efficiency, to encapsulate and protect the microlens elements from chemical and thermal processing damage, to minimize topographical underlayer variations which would axially misalign or otherwise aberrate microlens elements formed on non-planar surfaces, and, to complete the most difficult steps early in the process to minimize rework and scrap. A CMOS, CID, or CCD optoelectronic configuration is formed by photolithographically patterning a planar-array of photodiodes on a Silicon or other III-V, II-VI, or compound semiconductor substrate.

Abstract: It has been observed that, when a commercial plasma etcher is used for multiple etching tasks involving a variety of products, the amount of plasma damage incurred depends upon the chamber history of the etching tool. Thus, etching a gate sidewall spacer on a damage sensitive product, for example, in a MOSFET product with very thin gate oxide, may result in significant degradation of the gate oxide if the plasma etching tool had been used to etch vias on another type product in the preceding job. A method for monitoring and recording the chamber history and ascertaining the status of a plasma etching tool with regard to the tendency of said tool to introduce plasma damage in thin gate and tunnel oxide layers is disclosed. The method includes an a oxide damage monitor wafer which contains arrays of simple test devices. The monitor wafers can be partially formed and banked for later use. The test devices comprise a polysilicon plate partially covering a gate oxide.

Abstract: A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.

Abstract: A new method of cleaning metal precipitates after the etching of metal lines using a two-step process is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer wherein metal precipitates form at the interface between the barrier metal layer and the metal layer. The metal layer is covered with a layer of photoresist which is exposed to actinic light and developed and patterned to form the desired photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask to form metal lines whereby the metal precipitates are exposed on the surface of the barrier metal layer.

Abstract: The present invention provides a method of forming a Self-aligned contact with fewer process steps. The invention includes a three step insitu process of (1) a first descum step, (2) a dry etch step and (3) second descum step followed by (4) an isotropic etch step. The process comprises coating, exposing, and developing, and baking a photoresist layer over an insulating layer. In an important process stage, three steps are performed: (1) an insitu first descum step, (2) a dry etch step and (3) a second descum step. The dry etch step forms a first self-aligned contact opening. Next, the first contact opening is isotropically etched forming a smoother second contact opening 44. The photoresist layer 30 is then removed. Lastly, a metal layer 60 is deposited in said second self aligned contact opening 44. The invention reduces cycle time and eliminates several process steps while maintaining high yields. The smoother second contact opening 44 provides better metal adhesion.

Abstract: A method for anti-corrosion etching of metal interconnections, comprised in part of an aluminum layer, is achieved. The metal lines form self-aligned contacts (SAC) in contact openings in a polysilicon/metal dielectric (PMD) layer to a patterned underlying polysilicon layer. The method involves performing an oxygen ashing step in the same etching chamber immediately after etching the aluminum lines in a halogen gas, such as BCl.sub.3 and Cl.sub.2. This method using oxygen ashing avoids the use of the more traditional passivation gases CHF.sub.3 and CF.sub.4 which can overetch the polysilicon exposed in the SAC process that would cause electrical opens. And further, it avoids the formation of a polymer residue which is difficult to remove. The oxygen treatment reduces the Cl.sub.2 on the sidewalls of the Al lines, and also removes portions of the photoresist mask material containing Cl.sub.2. It is also easier to remove the remaining photoresist in a solvent stripping process.

Abstract: An improved method is described for planarizing dielectric layers which are formed between conductor layers in integrated circuits A three layer spin-on-glass sandwich is formed comprising a first silicon oxide layer, a spin-on-glass layer and a second silicon oxide layer. The improvement comprises performing an O.sub.2 plasma treatment on the first silicon oxide layer prior to forming the overlying spin-on-glass layer. The method prevents delamination (separation) between the first silicon oxide layer and the middle spin-on-glass layer.