Patents by Inventor Sheng-Lin Hung

Sheng-Lin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10671156
    Abstract: An electronic apparatus including an image capturing device, a storage device and a processor and an operation method thereof are provided. The image capturing device captures an image for a user, and the storage device records a plurality of modules. The processor is coupled to the image capturing device and the storage device and is configured to: configure the image capturing device to capture a head image of a user; perform a face recognition operation to obtain a face region; detect a plurality of facial landmarks within the face region; estimate a head posture angle of the user according to the facial landmarks; calculate a gaze position where the user gazes on the screen according to the head posture angle, a plurality of rotation reference angle, and a plurality of predetermined calibration positions; and configure the screen to display a corresponding visual effect according to the gaze position.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Acer Incorporated
    Inventors: Cheng-Tse Wu, An-Cheng Lee, Sheng-Lin Chiu, Ying-Shih Hung
  • Patent number: 10640372
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Publication number: 20200133389
    Abstract: The invention provides an operation method for multi-monitor applicable to an electronic system including a plurality of monitors. The operation method for multi-monitor includes capturing a current image including a user by using a camera, calculating a current gaze direction of the user according to the current image, and determining a target monitor according to the current gaze direction of the user. After the target monitor is determined, the operation method for multi-monitor further includes moving an object to a display area of the target monitor. In addition to the operation method for multi-monitor, an electronic system using the operation method is also provided.
    Type: Application
    Filed: May 12, 2019
    Publication date: April 30, 2020
    Applicant: Acer Incorporated
    Inventors: Sheng-Lin Chiu, Chao-Kuang Yang, An-Cheng Lee, Ying-Shih Hung, Cheng-Tse Wu
  • Publication number: 20200050263
    Abstract: An electronic apparatus including an image capturing device, a storage device and a processor and an operation method thereof are provided. The image capturing device captures an image for a user, and the storage device records a plurality of modules. The processor is coupled to the image capturing device and the storage device and is configured to: configure the image capturing device to capture a head image of a user; perform a face recognition operation to obtain a face region; detect a plurality of facial landmarks within the face region; estimate a head posture angle of the user according to the facial landmarks; calculate a gaze position where the user gazes on the screen according to the head posture angle, a plurality of rotation reference angle, and a plurality of predetermined calibration positions; and configure the screen to display a corresponding visual effect according to the gaze position.
    Type: Application
    Filed: October 3, 2018
    Publication date: February 13, 2020
    Applicant: Acer Incorporated
    Inventors: Cheng-Tse Wu, An-Cheng Lee, Sheng-Lin Chiu, Ying-Shih Hung
  • Patent number: 10559534
    Abstract: A circuit substrate includes a dielectric layer, a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive circuit and a first conductive via. The first conductive circuit is disposed on the dielectric layer. The first conductive via is disposed in the dielectric layer, and the first conductive circuit is connected to the first conductive via. The second conductive structure includes a second conductive circuit and a second conductive via. The second conductive circuit is disposed in the dielectric layer, the second conductive circuit and the first conductive circuit of the first conductive structure are arranged with an interval, and the second conductive via surrounds the first conductive via with an interval. The second conductive structure has an extending portion. The extending portion protrudes toward the first conductive via and does not contact the first conductive via.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 11, 2020
    Assignees: Industrial Technology Research Institute, First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd.
    Inventors: Sheng-Che Hung, Min-Lin Lee, Ching-Shan Chang, Hung-I Liu
  • Publication number: 20190345029
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Patent number: 10472232
    Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Patent number: 10340230
    Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Tsong-Lin Shen, Chen-Hsiao Wang, Sheng-Wei Hung, Chin-Tsai Chang, Hui-Lung Chou
  • Publication number: 20190189568
    Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Tsong-Lin Shen, Chen-Hsiao Wang, Sheng-Wei Hung, Chin-Tsai Chang, Hui-Lung Chou
  • Publication number: 20190148300
    Abstract: A circuit substrate includes a dielectric layer, a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive circuit and a first conductive via. The first conductive circuit is disposed on the dielectric layer. The first conductive via is disposed in the dielectric layer, and the first conductive circuit is connected to the first conductive via. The second conductive structure includes a second conductive circuit and a second conductive via. The second conductive circuit is disposed in the dielectric layer, the second conductive circuit and the first conductive circuit of the first conductive structure are arranged with an interval, and the second conductive via surrounds the first conductive via with an interval. The second conductive structure has an extending portion. The extending portion protrudes toward the first conductive via and does not contact the first conductive via.
    Type: Application
    Filed: August 2, 2018
    Publication date: May 16, 2019
    Applicants: Industrial Technology Research Institute, First Hi-tec Enterprise Co.,Ltd., NEXCOM International Co., Ltd.
    Inventors: Sheng-Che Hung, Min-Lin Lee, Ching-Shan Chang, Hung-I Liu
  • Patent number: 7372744
    Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 13, 2008
    Assignees: Kabushiki Kaisha Toshiba, Solid State System Co., Ltd.
    Inventors: Hitoshi Shiga, Chih-Chung Chen, Chih-Hung Wang, Sheng-Lin Hung
  • Publication number: 20060050314
    Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 9, 2006
    Inventors: Hitoshi Shiga, Chih-Chung Chen, Chih-Hung Wang, Sheng-Lin Hung