Abstract: A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A method for inspecting a screen includes sending image information to a screen, in which the screen includes plural color channels corresponding to colors, and the image information includes plural inspecting patterns corresponding to the colors of the color channels; displaying the inspecting patterns on the screen at the same time; capturing a picture on the screen by a capture device; fetching plural processing data by analyzing the captured picture according to the colors of the color channels; dichotomizing the processing data by brightness to obtain plural binary image data; and comparing the shapes shown by the binary image data to the shapes of the inspecting patterns of the image information.

Abstract: A seismic brace includes an elongated central brace unit and a rigid restraining member. The central brace unit has two ends adapted to be connected fixedly to a framework of a building, and a middle portion interconnecting the ends and having a cross-sectional area that is smaller than those of the ends. The restraining member is disposed around the middle portion of the central brace unit in a tight fit manner so as to prevent buckling of the central brace unit when the building is subjected to an earthquake, and includes two halves that are interconnected removably.

Abstract: A seismic brace includes an elongated central brace unit and a rigid restraining member. The central brace unit has two ends adapted to be connected fixedly to a framework of a building, and a middle portion interconnecting the ends and having a cross-sectional area that is smaller than those of the ends. The restraining member is disposed around the middle portion of the central brace unit in a tight fit manner so as to prevent buckling of the central brace unit when the building is subjected to an earthquake, and includes two halves that are interconnected removably.

Abstract: A seismic brace includes an elongated central brace unit and a rigid restraining member. The central brace unit has two ends adapted to be connected fixedly to a framework of a building, and a middle portion interconnecting the ends and having a cross-sectional area that is smaller than those of the ends. The restraining member is disposed around the middle portion of the central brace unit in a tight fit manner so as to prevent buckling of the central brace unit when the building is subjected to an earthquake, and includes two halves that are interconnected removably.