Patents by Inventor Sheng Lo
Sheng Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12353941Abstract: A method for near field communication with a serial transmission microcontroller and an NFC tag device using the same are provided in the present invention. The method includes: providing a serial interface microcontroller; capturing an NFC carrier signal from an NFC LC resonant circuit; performing a frequency division to the NFC carrier signal to obtain a NFC clock signal; filtering the NFC carrier signal from the NFC LC resonant circuit to obtain an envelope signal; sequentially receiving a digital sequence of the envelope signal according to triggering of the NFC clock signal based on a serial transmission protocol; and decoding an NFC data from the digital sequence based on an NFC transmission protocol rule.Type: GrantFiled: December 6, 2023Date of Patent: July 8, 2025Assignee: GENERALPLUS TECHNOLOGY INC.Inventors: Li Sheng Lo, Pei-Chien Hsu
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Publication number: 20250090487Abstract: The present invention relates to a topical anesthetic containing anesthetic agent-clay composite as the anesthetic agent in a delivery vehicle suitable for administration to the skin for increasing anesthetic agent permeation into the skin in order to decreasing onset time. In addition, the compositions of the invention have been shown to exhibit good storage stability with low ester type of anesthetic agent decomposition even at relatively high storage temperatures.Type: ApplicationFiled: September 9, 2021Publication date: March 20, 2025Applicants: ANDROS PHARMACEUTICALS CO., LTD., ANDROS PHARMACEUTICALS CO., LTD.Inventors: Yung-Chu CHEN, Chi-Sheng Lo, Mei-Wen Yen
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Publication number: 20250045894Abstract: An image quality evaluation system includes an image calibration device, an image capturing device, and a processing device. The image calibration device is placed in a scene and used for displaying a calibration pattern. The capturing device captures a first comparison image of the scene and the calibration pattern. The processing device is configured to obtain the first comparison image and a reference image containing the calibration pattern and compare the calibration pattern in the first comparison image and the reference image to generate calibration information. After being calibrated according to the calibration information, the image capturing device captures a second comparison image of the scene and the calibration pattern, and the processing device compares the calibration pattern in the second comparison image and the reference image to generate an image quality evaluation result.Type: ApplicationFiled: July 18, 2024Publication date: February 6, 2025Inventors: CHENG-YUAN CHANG, SHAU-SHENG LO, GUAN-WEN LIN, PO-CHING WU
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Publication number: 20240256802Abstract: A method for near field communication with a serial transmission microcontroller and an NFC tag device using the same are provided in the present invention. The method includes: providing a serial interface microcontroller; capturing an NFC carrier signal from an NFC LC resonant circuit; performing a frequency division to the NFC carrier signal to obtain a NFC clock signal; filtering the NFC carrier signal from the NFC LC resonant circuit to obtain an envelope signal; sequentially receiving a digital sequence of the envelope signal according to triggering of the NFC clock signal based on a serial transmission protocol; and decoding an NFC data from the digital sequence based on an NFC transmission protocol rule.Type: ApplicationFiled: December 6, 2023Publication date: August 1, 2024Inventors: Li Sheng LO, Pei-Chien HSU
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Publication number: 20240106757Abstract: A method of wireless signal transmission management includes transmitting a plurality of data packets to tethering equipment from user equipment to tethering equipment, determining a size of each of the plurality of data packets by the tethering equipment, designating data packets of the plurality of data packets having a specific range of sizes as control signal packets by the tethering equipment, and prioritizing in transmitting the control signal packets to a cellular network by the tethering equipment.Type: ApplicationFiled: September 21, 2023Publication date: March 28, 2024Applicant: MEDIATEK INC.Inventors: Ching-Hao Lee, Yi-Lun Chen, Ho-Wen Pu, Yu-Yu Hung, Jun-Yi Li, Ting-Sheng Lo
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Patent number: 11900196Abstract: A radio frequency identification integrated circuit for reducing pin counts and an RFID providing method thereof are provided in the present invention. The radio frequency identification integrated circuit includes a first IO pin, a second IO pin and a third IO pin. The method includes determining whether the coil is coupled to the first IO pin, the second IO pin and the third IO pin when the RFID IC is enabled; and determining the identification according to the voltage status of the non-coupled pin and the pins coupled to the coil.Type: GrantFiled: August 24, 2021Date of Patent: February 13, 2024Assignee: GENERALPLUS TECHNOLOGY INC.Inventors: Hsin Chou Lee, Li Sheng Lo, Hsien-Yao Li
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Patent number: 11442210Abstract: A polarizer substrate includes a substrate, a reflective layer, and a metal pattern layer. The reflective layer is located on the substrate and has a transmission area and a reflective area. The metal pattern layer is located on the reflective layer and the substrate. The metal pattern layer includes a polarizer structure and a microstructure. The polarizer structure includes a plurality of grid lines overlapping the transmission area. A thickness of each of the grid lines is 200 nm to 500 nm, a width of each of the grid lines is 30 nm to 70 nm, and a distance between each adjacent two of the grid lines is 30 nm to 70 nm. The microstructure overlaps the reflective area, and a thickness of the microstructure is 20 nm to 500 nm.Type: GrantFiled: July 20, 2020Date of Patent: September 13, 2022Assignee: Au Optronics CorporationInventors: Sheng-Kai Lin, Chia-Hsin Chung, Tsai-Sheng Lo, Sheng-Ming Huang, Ming-Jui Wang, Chih-Chiang Chen, Hui-Ku Chang, Cheng-Chan Wang, Chia-Po Lin, Jen-Kuei Lu
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Patent number: 11392003Abstract: An active device substrate including a substrate, first metal grid wires, a first transparent conductive layer, a gate insulating layer, a semiconductor layer, a source, and a drain is provided. The first metal grid wires are located on the substrate. The first transparent conductive layer includes a scan line and a gate connected to the scan line. The scan line and/or the gate is directly connected to at least a part of the first metal grid wires. The gate insulating layer is located on the first transparent conductive layer. The semiconductor layer is located on the gate insulating layer and overlapped with the gate. The source and the drain are electrically connected to the semiconductor layer.Type: GrantFiled: July 24, 2020Date of Patent: July 19, 2022Assignee: Au Optronics CorporationInventors: Cheng-Chan Wang, Tsai-Sheng Lo, Chia-Hsin Chung, Chih-Chiang Chen, Hui-Ku Chang, Sheng-Kai Lin, Chia-Po Lin, Ming-Jui Wang, Sheng-Ming Huang, Jen-Kuei Lu
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Patent number: 11336215Abstract: A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode.Type: GrantFiled: October 26, 2020Date of Patent: May 17, 2022Assignee: PEGATRON CORPORATIONInventors: Tai-Jung Huang, Pei-Chin Wang, Chien-Sheng Lo, Yu-Lin Fang, Yu-Ting Tsai
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Publication number: 20220138444Abstract: A radio frequency identification communication method for collision reduction with low power consumption and radio frequency identification communication system using the same are provided in the present invention. The radio frequency identification communication method includes the steps of: setting different delay periods according to different RFID tags; in each preset time, enabling a RFID reader and detecting whether a RFID tag is on the RFID reader; detecting whether there is only one RFID tag on the RFID reader; when two or more RFID tags on the RFID reader are detected in a specific time slot, entering a suspend mode to stop providing RF power such that the RFID tags perform power on reset when the reader is enabled next time.Type: ApplicationFiled: November 25, 2020Publication date: May 5, 2022Inventors: Hsien-Yao LI, Li Sheng LO
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Publication number: 20220067472Abstract: A radio frequency identification integrated circuit for reducing pin counts and an RFID providing method thereof are provided in the present invention. The radio frequency identification integrated circuit includes a first IO pin, a second IO pin and a third IO pin. The method includes determining whether the coil is coupled to the first IO pin, the second IO pin and the third IO pin when the RFID IC is enabled; and determining the identification according to the voltage status of the non-coupled pin and the pins coupled to the coil.Type: ApplicationFiled: August 24, 2021Publication date: March 3, 2022Inventors: Hsin Chou LEE, Li Sheng LO, Hsien-Yao LI
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Patent number: 11227834Abstract: A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.Type: GrantFiled: January 29, 2020Date of Patent: January 18, 2022Assignee: SEAGATE TECHNOLOGY LLCInventors: Karthik Chandrasekar, Ratnakar Dadi, Shawn Tzung-Sheng Lo, Emmanuel Atta, Alexander Tain, Subodh Yashwant Bhike
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Patent number: 11181769Abstract: A polarizer substrate includes a substrate, an organic planarization layer, an inorganic buffer layer, and a plurality of strip-shaped polarizer structures. The organic planarization layer is located on the substrate. The inorganic buffer layer is located on the organic planarization layer. The inorganic buffer layer has a plurality of trenches located on a first surface. The trenches do not penetrate through the inorganic buffer layer. The strip-shaped polarizer structures are located on the first surface of the inorganic buffer layer. Each of the trenches is located between two adjacent polarizer structures. A display panel is also provided.Type: GrantFiled: May 9, 2019Date of Patent: November 23, 2021Assignee: Au Optronics CorporationInventors: Tsai-Sheng Lo, Chih-Chiang Chen, Ming-Jui Wang, Sheng-Kai Lin, Sheng-Ming Huang, Chia-Hsin Chung, Hui-Ku Chang, Wei-Chi Wang, Jen-Kuei Lu
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Publication number: 20210255379Abstract: A polarizer substrate includes a substrate, a reflective layer, and a metal pattern layer. The reflective layer is located on the substrate and has a transmission area and a reflective area. The metal pattern layer is located on the reflective layer and the substrate. The metal pattern layer includes a polarizer structure and a microstructure. The polarizer structure includes a plurality of grid lines overlapping the transmission area. A thickness of each of the grid lines is 200 nm to 500 nm, a width of each of the grid lines is 30 nm to 70 nm, and a distance between each adjacent two of the grid lines is 30 nm to 70 nm. The microstructure overlaps the reflective area, and a thickness of the microstructure is 20 nm to 500 nm.Type: ApplicationFiled: July 20, 2020Publication date: August 19, 2021Applicant: Au Optronics CorporationInventors: Sheng-Kai Lin, Chia-Hsin Chung, Tsai-Sheng Lo, Sheng-Ming Huang, Ming-Jui Wang, Chih-Chiang Chen, Hui-Ku Chang, Cheng-Chan Wang, Chia-Po Lin, Jen-Kuei Lu
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Publication number: 20210247652Abstract: An active device substrate including a substrate, first metal grid wires, a first transparent conductive layer, a gate insulating layer, a semiconductor layer, a source, and a drain is provided. The first metal grid wires are located on the substrate. The first transparent conductive layer includes a scan line and a gate connected to the scan line. The scan line and/or the gate is directly connected to at least a part of the first metal grid wires. The gate insulating layer is located on the first transparent conductive layer. The semiconductor layer is located on the gate insulating layer and overlapped with the gate. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: July 24, 2020Publication date: August 12, 2021Applicant: Au Optronics CorporationInventors: Cheng-Chan Wang, Tsai-Sheng Lo, Chia-Hsin Chung, Chih-Chiang Chen, Hui-Ku Chang, Sheng-Kai Lin, Chia-Po Lin, Ming-Jui Wang, Sheng-Ming Huang, Jen-Kuei Lu
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Publication number: 20210248341Abstract: A photosensitive device includes a display panel, a photosensitive element substrate, and a first quarter wave plate. The photosensitive element substrate is located on the back of the display panel. The photosensitive element substrate includes a first substrate, a plurality of first light emitting diodes, a plurality of photosensitive elements, and a first polarizer structure. The first light emitting diodes and the photosensitive elements are located on the first substrate. The first polarizer structure is located on the first light emitting diodes and the photosensitive elements. The first quarter wave plate is located between the first polarizer structure and the display panel.Type: ApplicationFiled: July 21, 2020Publication date: August 12, 2021Applicant: Au Optronics CorporationInventors: Chia-Po Lin, Tsai-Sheng Lo, Chih-Chiang Chen, Sheng-Ming Huang, Sheng-Kai Lin, Ming-Jui Wang, Chia-Hsin Chung, Hui-Ku Chang, Cheng-Chan Wang, Jen-Kuei Lu
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Publication number: 20210233845Abstract: A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.Type: ApplicationFiled: January 29, 2020Publication date: July 29, 2021Inventors: Karthik Chandrasekar, Ratnakar Dadi, Shawn Tzung-Sheng Lo, Emmanuel Atta, Alexander Tain, Subodh Yashwant Bhike
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Patent number: 11054740Abstract: An imprint mold and a method for manufacturing the same are provided. The imprint mold includes a plurality of substantially identical or different mold patterns, wherein there isn't any height difference between the mold patterns.Type: GrantFiled: September 10, 2018Date of Patent: July 6, 2021Assignee: AU OPTRONICS CORPORATIONInventors: Sheng-Ming Huang, Sheng-Kai Lin, Chih-Chiang Chen, Hui-Ku Chang, Chia-Hsin Chung, Wei-Chi Wang, Ming-Jui Wang, Jen-Kuei Lu, Tsai-Sheng Lo, Huang-Kai Shen
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Publication number: 20210152114Abstract: A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode.Type: ApplicationFiled: October 26, 2020Publication date: May 20, 2021Applicant: PEGATRON CORPORATIONInventors: Tai-Jung Huang, Pei-Chin Wang, Chien-Sheng Lo, Yu-Lin Fang, Yu-Ting Tsai