Abstract: Semiconductor devices, methods, and memory systems for managing logic units are provided. In one aspect, a semiconductor device includes a logic unit associated with an identifier (ID). The logic unit includes a control logic and a reporting unit coupled to the control logic. The semiconductor device also includes a control interface coupled to the reporting unit. The control logic is configured to: receive, from the control interface, an enumeration command in an iteration; drive, using the reporting unit, one or more bits of the ID to the control interface; and in response to determining that a received bit from the control interface mismatches a driven bit of the ID, stop driving one or more additional bits of the ID to the control interface.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.

Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.

Abstract: A host device receives, from a memory device, secure data that includes a first content block and a second content block. Upon determining that the first content block is encrypted, the host device decrypts the first content block to obtain corresponding first plaintext data. Upon determining that the second content block is unencrypted, the host device obtains corresponding second plaintext data from the second content block. When the reception of secure data from the memory device is completed, the host device obtains a first signature from a signature block sent along with the secure data. The host device computes a second signature on the plaintext data obtained by the host device, and compares the first signature to the second signature. If the host device determines that the first signature is equal to the second signature, then the host device accepts the plaintext data as legitimate.

Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.