Abstract: A test device is configured to test an on-chip clock controller having a debug function. The test device includes a scan chain and a test circuit. The scan chain includes N flip-flop circuit(s), each of which stores a first input signal as a storage signal, then stores a second input signal as the storage signal or keeps the current storage signal according to an input clock, and then output the storage signal. Since the first and second input signals are different, the outputted storage signal indicates whether the flip-flop circuit stores the second input signal or keeps the current storage signal according to the input clock under predetermined test setting, and indicates whether circuits under test (CUTs) for transmitting the input clock operate normally. The test circuit outputs an observation clock of the on-chip clock controller or an independent clock as the input clock according to the predetermined test setting.

Abstract: A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether an error exists in the plurality of scan chains or not according to the plurality of scan output data by a decoding circuit.

Abstract: A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether the plurality of scan chains exist an error according to the plurality of scan output data by a decoding circuit.

Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.

Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.