Patents by Inventor Sheng Ren

Sheng Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210041753
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Publication number: 20210041756
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Publication number: 20210041754
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Publication number: 20210041755
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Patent number: 10879458
    Abstract: A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 10852609
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 1, 2020
    Assignee: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Publication number: 20200371586
    Abstract: A computing device having a front-facing camera applies facial landmark detection and identifies eye regions in the digital image responsive to the front-facing camera capturing a digital image of an individual. For at least one of the eye regions, the computing device is further configured to extract attributes of the eye region, determine an eye gaze score based on the extracted attributes, generate a modified eye region based on the eye gaze score, and output a modified digital image with the modified eye region.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 26, 2020
    Inventors: SiPin WENG, Sheng-Xiang CHEN, Chung Ren YAN
  • Patent number: 10823683
    Abstract: A method for detecting defects in deep features like channel holes, via holes or trenches based on laser-enhanced electron tunneling effect. A substrate having thereon a film stack is provided. First and second deep features are formed in the film stack. The first deep feature has a sacrificial oxide layer disposed at its bottom. The second deep feature comprises an under-etch defect. The sacrificial oxide layer has a thickness of less than 50 angstroms. The substrate is subjected to a laser-enhanced electron beam inspection process. The substrate is scanned by an electron beam and illuminated by a laser beam. The laser beam induces electron tunneling across the sacrificial protection layer, thereby capturing a bright voltage contrast (BVC) signal corresponding to the first deep feature, and detecting a dark voltage contrast (DVC) signal corresponding to the second deep feature.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 3, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Sheng Chao Nie, Jin Xing Chen, Junqi Ren
  • Publication number: 20200327417
    Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.
    Type: Application
    Filed: March 17, 2020
    Publication date: October 15, 2020
    Applicant: NVIDIA Corp.
    Inventors: Zhiyao Xie, Haoxing Ren, Brucek Khailany, Sheng Ye
  • Publication number: 20200272010
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 27, 2020
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Publication number: 20200266339
    Abstract: A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Hui-Hsien WEI, Wei-Chih WEN, Pin-Ren DAI, Chien-Min LEE, Sheng-Chih LAI, Han-Ting TSAI, Chung-Te LIN
  • Publication number: 20200266338
    Abstract: A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Hui-Hsien WEI, Wei-Chih WEN, Pin-Ren DAI, Chien-Min LEE, Sheng-Chih LAI, Han-Ting TSAI, Chung-Te LIN
  • Publication number: 20200252832
    Abstract: This application provides a packet sending method, applied to a communications system including at least two nodes, the at least two nodes include at least one parent node having a child node, a packet sent by the child node is forwarded by the parent node, and the method includes: receiving, by a first node, first instruction information, where the first instruction information is used to instruct the first node to send a packet after a first moment, and the first node is a parent node; and sending, by the first node, a first packet according to the first instruction information.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Shoushou Ren, Bing Liu, Chuang Wang, Delei Yu, Sheng Jiang
  • Patent number: 10644231
    Abstract: A method for fabricating a memory device includes forming a resistance switching element over a bottom electrode; forming a top electrode over the resistance switching element; forming a first spacer covering a sidewall of the resistance switching element; forming a second spacer surrounding the first spacer and exposing the top electrode; and forming a metallization pattern connected with the top electrode and the second spacer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 10632688
    Abstract: A method for fabricating flexible microfluidic chips with plastic membranes. In particular, the present invention provides a single-step method for microchannel fabrication of microfluidic chips in a fast and cost-efficient manner.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 28, 2020
    Assignees: Hong Kong Baptist University, THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Kangning Ren, Dik-Lung Ma, Chong Hu, Wanbo Li, Sheng Lin, Hongkai Wu
  • Publication number: 20200123380
    Abstract: A process for preparing a TPU alloy material through in-situ compatibilization includes: 1) adding a premixed TPU raw material to a feeding port of a twin-screw extruder; injecting a mixture of an alloy component and a dual-active substance into the twin-screw extruder through a lateral feeding port; adding an auxiliary reagent to the TPU raw material or the mixture of the alloy component and the dual-active substance, wherein the alloy component is a polyolefin or a thermoplastic polymer material having reactivity, wherein the dual-active substance is a substance containing a group reactive with the TPU raw material and a group reactive with the alloy component, and the auxiliary reagent includes an initiator; 2) controlling a temperature of a reaction zone of the twin-screw extruder at 50° C. to 250° C., and granulating an extruded material by underwater cutting; and 3) drying the granulated product to obtain the TPU alloy material.
    Type: Application
    Filed: February 24, 2017
    Publication date: April 23, 2020
    Applicant: Miracll Chemicals Co., Ltd.
    Inventors: Zhensheng Zhan, Hongwei Song, Qingbo Zhao, Sheng Zhang, Guanglei Ren
  • Patent number: 10625446
    Abstract: A high-temperature hot-pressing molding machine includes a mold unit, a heating, unit disposed to heat the mold unit, a heat insulating unit including a surrounding insulating member to enclose the mold unit and two insulating layers disposed on two opposite sides of the mold unit to obstruct heat radiation and conduction from the mold unit, a heat dissipating unit disposed on the insulating layers, a cooling unit disposed on the heat dissipating unit, and a vacuum unit disposed to form a vacuum space. Under a vacuum environment, with the heat insulating unit defining a heat zone containing the mold unit, other component parts adjacent to the heat zone can be prevented from damage in a high temperature operation.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 21, 2020
    Assignee: National Formosa University
    Inventors: Shu-Huei Hsieh, Yi-Ren Tzeng, Sheng-Hsiang Chiang, Wen-Chen Liao
  • Patent number: 10522834
    Abstract: A multiple-element composite material for negative electrodes, a preparation method therefor, and a lithium-ion battery using the negative electrode material. The lithium-ion battery uses multiple-element composite material for negative electrodes has a core-shell structure containing multiple shell layers. The inner core consists of graphite and nano-active matter coating the surface of the graphite. The outer layers of the inner core are in order: the first shell layer is of an electrically conductive carbon material, the second shell layer is of a nano-active matter, and the third shell layer is an electrically conductive carbon material coating layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 31, 2019
    Assignee: Shenzhen BTR New Energy Materials Inc.
    Inventors: Min Yue, Peng He, Sheng Li, Jianguo Ren, Youyuan Huang
  • Patent number: 10509874
    Abstract: A method for forecasting thermal runaway safety of a full battery by a computer is provided and including receiving a self heat generation onset temperature T0 of a first power battery, wherein the first power battery is a half cell; calculating a maximum temperature Tmax of thermal runaway of the first power battery based on a thermal runaway reaction kinetic model stored in the computer, calculating a maximum temperature rise ?T by making difference between the maximum temperature Tmax and the self heat generation onset temperature T0; and judging the thermal runaway safety of the first power battery by the relationship between the self heat generation onset temperature T0 and the maximum temperature rise ?T.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 17, 2019
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Xu-Ning Feng, Si-Qi Zheng, Xiang-Ming He, Li Wang, Ming-Gao Ouyang, Dong-Sheng Ren, Lan-Guang Lu
  • Publication number: 20190374730
    Abstract: A nebulizer with orientation independent operation is provided. The nebulizer includes an outer tube, an inner tube provided in the outer tube, and a mesh structure disposed above an end of the outer tube. A first channel, a main channel, and a second channel are formed between the outer tube and the inner tube. When in use, capillary force is created in the main channel, such that a liquid contained in the inner tube can be transported sequentially through the second channel, the main channel, and the first channel to the mesh structure. The liquid is nebulized and dispersed into the air through vibrations of the mesh structure actuated by an annular vibration source.
    Type: Application
    Filed: October 19, 2018
    Publication date: December 12, 2019
    Inventors: Chih-Chieh Chen, Sheng-Hsiu Huang, Chih-Wei Lin, Yu-Mei Kuo, Wei-Ren Ke