Patents by Inventor Sheng Tang

Sheng Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250106743
    Abstract: An out-of-service recovery search method includes establishing a frequency list including at least one searchable frequency, searching a suitable cell of a network according to the frequency list when the user terminal is in an out-of-service state, determining at least one first skip condition of the user terminal, performing a full-band power scan mechanism for scanning received signal strength indication (RSSIs) of user terminal supported frequency bands when the at least one first skip condition of the user terminal is absent and no suitable cell of the network is searched within the searchable frequency of the frequency list, skipping the full-band power scan mechanism when the at least one first skip condition of the user terminal is present and no suitable cell of the network is searched within the searchable frequency, and performing an RSSI sniffer for scanning a signal power of each frequency of the searchable frequency.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Applicant: MEDIATEK INC.
    Inventors: Jia-Hao Wu, Tzyuan Shiu, Da-Wei Wang, Lu-Chi Lin, Mu-Chi Fang, Wen-Yang Chou, Tsung-Sheng Tang, Chung-Pi Lee
  • Publication number: 20250099495
    Abstract: Method of at least partially inhibiting the function of Klebsiella pneumoniae carbapenemase-2 (KPC-2) or a variant thereof, the method including contacting the KPC-2 with a benzoxaborole selected from the group consisting of 5-chloro-1,3-dihydro-1-hydroxy-2,1-benzoxaborole, 5-fluoro-1,3-dihydro-1-hydroxy-2,1-benzoxaborole, and mixtures thereof useful in the treatment of beta-lactam antibiotic resistant bacteria infections in a subject.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Yang TANG, Chen YANG, Chenyu LIU, Sheng CHEN
  • Publication number: 20250095134
    Abstract: The present disclosure discloses a method and system for visual inspection of a target product. The method includes a) receiving an image associated with the target product; generating a plurality of region of interests (ROIs) associated with the image; identifying, based on the plurality of non-terminal ROIs, a first set of features and a second set of features associated with the image. The first set of features and the second set of features are indicative of one of a presence of defect within the image or an absence of defect within the image. The method also includes determining, based on the first set of features and the second set of features, a result of the visual inspection of the target product associated with the image. The result is a success result or a failure result.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Inventors: Andre IVAN, Zong Sheng TANG, Ariel BECK
  • Publication number: 20250094744
    Abstract: There is provided an antenna for a radio frequency identification (RFID) tag, which includes a loop antenna, an amplifying antenna, an additional antenna structure to modify impedance of the entire antenna. The additional antenna structure has a first electromagnetic coupling with the amplifying antenna and a second electromagnetic coupling with the loop antenna.
    Type: Application
    Filed: September 27, 2024
    Publication date: March 20, 2025
    Inventors: Jing Jung Tang, Leung Chiu, Xiao Sheng Chen
  • Publication number: 20250087404
    Abstract: Structures, devices, and methods for wireless power transfer systems are described. A structure can include a plurality of strands arranged into a first coil layer and a second coil layer. The plurality of strands can be formed on a parallel path surrounding a center of the structure. The plurality of strands can extend away from the center on the first coil layer. The plurality of strands can extend towards the center on the second coil layer. For every fixed interval along a length of the structure, a first strand among the plurality of strands can be looped from the first coil layer to the second coil layer and a second strand among the plurality of strands can be looped from the second coil layer to the first coil layer.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 13, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Sheng Yuan, Shangfeng Jiang, Weiwei Zhou, Jiangjian Huang, Bo Tang
  • Publication number: 20250079069
    Abstract: Structures, devices, and methods for wireless power transfer systems are described. A structure can include a plurality of strands a plurality arranged into a coil layer. For every fixed interval along a length of the structure, the plurality of strands can be folded at a lateral angle and vertically inverted in response to being folded at the lateral angle. The plurality of strands being folded can cause the plurality of strands to surround a center of the structure in a parallel path.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 6, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Sheng Yuan, Shangfeng Jiang, Weiwei Zhou, Jiangjian Huang, Bo Tang, Hulong Zeng
  • Publication number: 20250079890
    Abstract: A wireless power apparatus may include a power receiver having an elongated core member with a long axis and a receiver conductor wound spirally around the elongated core member to form an elongated receiver coil, the power receiver configured to receive power from a power transmitter having a transmitter conductor being wound circularly around a center point and disposed in a plane to form a planar transmitter coil, the planar transmitter coil configured to be connected to an alternating current power source to wirelessly transmit power, the planar transmitter coil having a transmitter coil radial axis starting at the center point and defining a transmitting region from an inner edge of the planar transmitter coil to an outer edge of the planar transmitter coil along the transmitter coil radial axis.
    Type: Application
    Filed: December 30, 2022
    Publication date: March 6, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Sheng Yuan, Jiangjian Huang, Bo Tang, Hulong Zeng
  • Publication number: 20250081730
    Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.
    Type: Application
    Filed: June 26, 2024
    Publication date: March 6, 2025
    Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
  • Publication number: 20250075979
    Abstract: The present application provides a fixing apparatus for a furnace wire of a furnace body heater, which is formed by assembling a plurality of fixing units. A structure of each of the fixing units includes: a front end structure and a tail end structure connected together. The front end structure is provided with a first recess and a second recess. The tail end structure is provided with a third recess and a fourth protrusion block. Two adjacent ones of the fixing units form a first splice structure, in the first splice structure, the fourth protrusion block of the fixing unit at the top is snap fitted in the third recess of the fixing unit at the bottom to achieve fixation. An opening of a first recess of the fixing unit at the bottom and an opening of a second recess of the fixing unit at the top are butt-jointed together.
    Type: Application
    Filed: April 10, 2024
    Publication date: March 6, 2025
    Applicant: Shanghai Huali Microelectronics Corporation
    Inventor: Sheng Tang
  • Patent number: 12241174
    Abstract: A method used to repair a workpiece through a combination of laser and an electrochemical reaction is provided. A tool anode is arranged on the back side of the workpiece and is spaced therefrom. A laser beam is focused on an outer surface of the workpiece to realize localized repairing on the back side. The method realizes localized coating repairing on the back side of the workpiece through coordination between the thermal effect of the laser and the electrochemical deposition based on the characteristic of high thermal conductivity of the workpiece. The electrodeposition reaction does not occur in regions that do not need to be repaired. The operating process is simple, the cost of the plating solution is largely reduced, and the problem that the coating on the inner wall of the thin-walled workpiece is difficult to repair due to stripping is solved.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 4, 2025
    Assignee: JIANGSU UNIVERSITY
    Inventors: Kun Xu, Zhihao Leng, Yangfan Tang, Sheng Guo, Zhaoyang Zhang, Hao Zhu, Yang Liu, Yucheng Wu, Wenhui Liang, Panzhou Li
  • Publication number: 20250061346
    Abstract: A method of determining interaction information, an electronic device and a storage medium are provided, which relates to a field of artificial intelligence technology, in particular to a large model, a generative model, an NLP, an intelligent search and other fields. An implementation is to determine a plurality of questioning dimensions according to query information of a subject and historical query information, where each questioning dimension includes a dimension name and a plurality of options; determine a target questioning dimension from the plurality of questioning dimensions according to evaluation values of the plurality of questioning dimensions and whether semantic information of the plurality of questioning dimensions are consistent with semantic information of a query result associated with the query information; and determine the interaction information according to the dimension name and the plurality of options in the target questioning dimension.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Applicant: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Xiao LI, Xin JIA, Simiu GU, Junfeng WANG, Haibo SHI, Yu LU, Sheng XU, Liang ZHANG, Wenjie ZHOU, Yijun LIU, Mei LU, Zichen WU, Min YANG, Huanjie WANG, Qiao TANG, Mengmeng CUI
  • Patent number: 12223379
    Abstract: A fluid-tight envelope (13) encloses an RFID chip (11), a first array of conductors (14a-d) on an internal surface (19), and a second array of conductors (15a-d) fixed to an opposing internal surface (20) of a flexible outer wall (22) of the envelope (13). The outer wall (22) is urged inwardly by ambient pressure to press the conductors of the second array (15a-d) into electrical contact with the conductors of first array (14a-d) to thereby form an antenna (12). Fluid pressure in the chamber (21) that holds the antenna (12) tends to displace the outer wall (22) outwardly to thereby separate conductors of the first and second arrays (14a-d, 15a-d).
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: February 11, 2025
    Assignee: LOGISTICS AND SUPPLY CHAIN MULTITECH R&D CENTRE LIMITED
    Inventors: Feng Lu, Xiao Sheng Chen, Jing Jung Tang
  • Publication number: 20250041340
    Abstract: The present invention provides a method of treating targeted abnormal cells that are resistant, refractory, insensitive, non-responsive, or inadequately responsive to an ingredient, as well as cytotoxic cells used therein, comprising administering an effective amount of the ingredient-complexed cytotoxic cells to a subject with the disease.
    Type: Application
    Filed: December 12, 2022
    Publication date: February 6, 2025
    Applicant: Acepodia Biotechnologies Ltd.
    Inventors: CHING-WEN HSIAO, ZIH-FEI CHENG, TAI-SHENG WU, YAN-LIANG LIN, HAO-KANG LI, SAI-WEN TANG, HSIU-PING YANG, SHIH-CHIA HSIAO
  • Patent number: 12205840
    Abstract: A horizontally oriented calibration jig for a wafer gripper arm of an ion implanter is disclosed. The calibration jig is mounted within the process chamber of the ion implanter. The calibration jig includes a mounting plate that spans a diameter of the wafer gripper arm, a support stand passing through the mounting plate, and a calibration plate at a bottom end of the support stand. The perimeter of the calibration plate includes a plurality of notches. The calibration plate is rotated. If any finger of the wafer gripper arm falls into a notch, the rotating calibration plate stops. The finger is then adjusted until it does not fall into a notch.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lung-Yin Tang, Tsung-Min Lin, Hsin-Sheng Liang
  • Patent number: 12164672
    Abstract: Systems, computer program products, and methods are described herein for analyzing micro-anomalies in anonymized electronic data. The present disclosure is configured to import or retrieve a first data set, process the first data set to develop at least one event-outcome projection, define an outcome projection data set, import or receive a monitored user data set, anonymize the monitored user data set, define an avatar data set process the avatar data set, wherein the steps of import or receive a monitored user data set, anonymize the monitored user data set, and define an avatar data set are repeated one or more times.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: December 10, 2024
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Jennifer Tiffany Renckert, Daniel Joseph Serna, Frank J. Yanan, Jeffrey Kyle Johnson, Benjamin Tweel, Jake Michael Yara, Robert Cain Durbin, Jr., Sheng Tang Hsiang, Jack Lawson Bishop, III, James J. Siekman
  • Publication number: 20240405100
    Abstract: An integrated circuit includes a device region and an overlay mark region. The device region includes a plurality of stacked channels of a transistor, a source/drain region of the transistor, a source/drain contact of a first material on the source/drain region, and a conductive via of a second material in contact with the source/drain contact. The overlay mark region includes a first diffraction grating of first metal structures of the first material and a second first diffraction grating of second metal structures above of the second material above and offset from the first metal structures.
    Type: Application
    Filed: October 6, 2023
    Publication date: December 5, 2024
    Inventors: Pei-Sheng TANG, Chen-Yen KAO, Jheng-Syun YANG
  • Publication number: 20240389353
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Sheng TANG, Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240363398
    Abstract: A semiconductor die is provided. The semiconductor die includes a substrate having a front surface, a rear surface opposite to the front surface, and a sidewall connected between the front surface and the rear surface. The sidewall includes a first primary segment immediately connected to the front surface, a second primary segment immediately connected to the rear surface, and a middle segment between the first primary segment and the second primary segment. The slope of the second primary segment is less than the slope of the first primary segment, and the slope of the middle segment is less than the slope of the second primary segment. Each of the first primary segment, the second primary segment, and the middle segment is a flat surface having a slope greater than 0 degrees relative to a line parallel to the front surface of the substrate.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
  • Publication number: 20240350650
    Abstract: A linker, comprising an Lb structure fragment, the Lb structure being selected from the following formula, wherein subscript q is selected from any integer from 1 to 20, preferably from 3 to 10, and most preferably from 5 to 8. The present application also relates to a use of the linker in the preparation of a linker-drug and a ligand-drug conjugate.
    Type: Application
    Filed: May 19, 2022
    Publication date: October 24, 2024
    Applicant: BEIJING HOPE PHARMACEUTICAL CO.LTD.
    Inventors: Haining LV, Yingzhao WANG, Changru LIU, Yanling LIU, Sheng TANG, Chunxia LI, Mingsheng ZHAI, Jiuquan YANG, Bojing LIU, Hongyun LI
  • Patent number: 12120886
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Sheng Tang, Wei-De Ho, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin