Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon layer; depositing a dielectric layer on the wafer to cover a gate module of the IC device; smoothing the dielectric; implanting ions to form a defect layer; cutting the wafer into individual silicon dies; preparing a glass panel and the silicon dies for bonding; bonding the silicon dies onto the glass panel to form a bonded structure; annealing the bonded structure; splitting the bonded structure along the defect layer; removing the remaining silicon layer from the silicon substrate and relaxed SiGe layer on the silicon die on the glass panel; and completing the glass panel circuitry.

Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

Abstract: A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross-point is formed between the bottom word line and the bit line and a second cross-point is formed between the bit line and the top word line. A resistive memory material is provided at each cross-point above and below the bit line. A diode is formed at each cross-point between the resistive memory material and either the top word line or the bottom word line, respectively.

Abstract: A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.

Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

Abstract: A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

Abstract: A method of selectively depositing a ferroelectric thin film on an indium-containing substrate in a ferroelectric device includes preparing a silicon substrate; depositing an indium-containing thin film on the substrate; patterning the indium containing thin film; annealing the structure; selectively depositing a ferroelectric layer by MOCVD; annealing the structure; and completing the ferroelectric device.

Abstract: A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

Abstract: A method of fabricating a multi-level 3D memory array includes: preparing a wafer and peripheral circuits thereon; layers of metal, memory resistor material, and metal are deposited, patterned and etched. The steps of the method of the invention are repeated for N levels of a memory array.

Abstract: A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.

Abstract: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

Abstract: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxia

Abstract: A SiGe surface-normal optical path photodetector structure and a method for forming the SiGe optical path normal structure are provided. The method comprises: forming a Si substrate with a surface; forming a Si feature, normal with respect to the Si substrate surface, such as a via, trench, or pillar; depositing SiGe overlying the Si normal feature to a thickness in the range of 5 to 1000 nanometers (nm); and, forming a SiGe optical path normal structure having an optical path length in the range of 0.1 to 10 microns. Typically, the SiGe has a Ge concentration in the range from 5 to 100%. The Ge concentration may be graded to increase with respect to the deposition thickness. For example, the SiGe may have a 20% concentration of Ge at the Si substrate interface, a 30% concentration of Ge at a SiGe film top surface, and a thickness of 400 nm.

Abstract: Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatably with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit for generating a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Abstract: An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

Abstract: Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatably with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit for generating a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

Abstract: A method is provided for forming a single-phase c-axis PGO film overlying a Pt metal electrode. Although the method is summarized in the context of a Pt bottom electrode, it has a broader application to other noble metals. The method comprises: forming a bottom electrode mixture of Pt and Pt3O4; forming a single-phase c-axis PGO thin film overlying the bottom electrode; and, forming a top electrode overlying the PGO thin film. Forming a bottom electrode mixture of a Pt and Pt3O4 includes: forming a Pt first layer; and, forming a second layer, interposed between the first layer and the PGO thin film, of fully oxidized Pt3O4. In other aspects, forming a bottom electrode mixture of Pt and Pt3O4 includes forming a polycrystalline mixture of Pt and Pt3O4. A c-axis PGO film capacitor is also provided. Again, a Pt bottom electrode is described, along with other noble metal bottom electrodes.

Abstract: A method of forming PrXCa1-xMnO3 thin films having a PMO/CMO super lattice structure using metalorganic chemical vapor deposition includes preparing organometallic compounds and solvents and mixing organometallic compounds and solvents to form PMO and CMO precursors. The precursors for PMO and CMO are injected into a MOCVD chamber vaporizer. Deposition parameters are selected to form a nano-sized PCMO thin film or a crystalline PCMO thin film from the injection of PMO and CMO precursors, wherein the PMO and CMO precursors are alternately injected into the MOCVD chamber vaporizer. The selected deposition parameters are maintained to deposit the PCMO thin film species having a desired Pr:Ca concentration ratio in a specific portion of the PCMO thin film. The resultant PCMO thin film is annealed at a selected temperature for a selected time period.