Patents by Inventor Sheng-Tou Tseng

Sheng-Tou Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658046
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: May 23, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ting-Yeh Wu
  • Patent number: 11587808
    Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 21, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ying-Lin Chen, Ting-Yeh Wu
  • Patent number: 11410945
    Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 9, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ying-Lin Chen, Ting-Yeh Wu
  • Publication number: 20210288003
    Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.
    Type: Application
    Filed: November 10, 2020
    Publication date: September 16, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ying-Lin CHEN, Ting-Yeh WU
  • Publication number: 20210217632
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Application
    Filed: November 10, 2020
    Publication date: July 15, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ting-Yeh WU
  • Publication number: 20210217641
    Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.
    Type: Application
    Filed: August 20, 2020
    Publication date: July 15, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ying-Lin CHEN, Ting-Yeh WU
  • Publication number: 20190275600
    Abstract: A flux transfer tool includes a flux tray, a baseplate, a flux transfer head and a flexible member. The baseplate is disposed on the flux tray. The baseplate has a plurality of holes formed thereon. The flux transfer head is arranged corresponding to the flux tray and configured to move with respect to the flux tray. The flexible member is disposed on the flux transfer head. The flexible member faces the baseplate when the flux transfer head is located above the flux tray. When the holes are filled with a flux, the flux transfer head moves towards the flux tray, such that the flexible member adsorbs the flux from the holes.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 12, 2019
    Inventors: Kun-Chi Hsu, Sheng-Tou Tseng, Hung-Chieh Huang
  • Publication number: 20190267346
    Abstract: A flux transfer tool includes a heater, a flux supplier, an ejector and a baseplate. The heater has a nozzle. The flux supplier is connected to the heater and contains a flux. The ejector is connected to the heater. The baseplate has a plurality of first holes formed thereon. The flux supplier supplies the flux to the heater, the heater heats the flux, and the ejector ejects the flux from the nozzle to spray the flux on the baseplate.
    Type: Application
    Filed: February 28, 2018
    Publication date: August 29, 2019
    Inventors: Kun-Chi Hsu, Sheng-Tou Tseng, Hung-Chieh Huang
  • Publication number: 20190247944
    Abstract: A flux transfer tool includes a frame, a plunger, a baseplate, a flux supplier and a driving mechanism. The frame has a chamber. The plunger is movably disposed in the chamber. The baseplate is mounted on the frame. The baseplate has a plurality of holes formed thereon. The flux supplier is connected to the frame and contains a flux. The flux supplier supplies the flux to the chamber between the plunger and the baseplate. The driving mechanism is disposed on the frame. The driving mechanism drives the plunger to move towards the baseplate to squeeze the flux out of the holes of the baseplate. The driving mechanism drives the plunger to move away from the baseplate to keep the flux in the chamber.
    Type: Application
    Filed: February 11, 2018
    Publication date: August 15, 2019
    Inventors: Kun-Chi Hsu, Sheng-Tou Tseng, Hung-Chieh Huang
  • Publication number: 20190229064
    Abstract: A laser color marking method for a semiconductor package has steps of: (a) providing a semiconductor element; (b) sputtering a metal layer on the semiconductor element; (c) obtaining a marking pattern; and (d) applying a laser light source on the marking region to form a mark according to the marking pattern. The mark is consisted of an optical oxide film converting ambient light to a corresponding color light, so a visible color mark is marked. Therefore, the present invention easily laser-marks the visible color mark on the semiconductor package.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 25, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Chin-Ta Wu, Sheng-Tou Tseng, Kuo-Jhan Kao, Ying-Lin Chen, Cheng-Hung Song, Hung-Chieh Huang, Kun-Chi Hsu
  • Publication number: 20190134742
    Abstract: A method for laser marking includes steps of forming a test matter on a substrate; using a laser to form a laser path on the test matter; determining whether at least one of a first condition and a second condition occurs, wherein the first condition is a color of an abnormal area on the laser path is different from a color of the laser path and the second condition is a width of the abnormal area is larger than a width of the laser path; and when the at least one of the first condition and the second condition occurs, adjusting at least one laser parameter of the laser to prevent the at least one of the first condition and the second condition from occurring.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 9, 2019
    Inventors: Yun-Chieh Fang, Sheng-Tou Tseng, Cheng-Hung Song, Sung-Hua Yang