Patents by Inventor Sheng-Wei Hung

Sheng-Wei Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating MEMS device integrated with a semiconductor integrated circuit
    Patent number: 10640372
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • METHOD FOR FABRICATING MEMS DEVICE INTEGRATED WITH A SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20190345029
    Abstract: A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • MEMS device integrated with a semiconductor integrated circuit and manufacturing method thereof
    Patent number: 10472232
    Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang
  • Semiconductor chip
    Patent number: 10340230
    Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Tsong-Lin Shen, Chen-Hsiao Wang, Sheng-Wei Hung, Chin-Tsai Chang, Hui-Lung Chou
  • SEMICONDUCTOR CHIP
    Publication number: 20190189568
    Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Tsong-Lin Shen, Chen-Hsiao Wang, Sheng-Wei Hung, Chin-Tsai Chang, Hui-Lung Chou
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20180162725
    Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Tsong-Lin Shen, Chien-Chung Su, Chih-Cheng Wang, Yu-Chih Chuang, Sheng-Wei Hung, Min-Hung Wang, Chin-Tsai Chang