Abstract: This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.

Abstract: This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.