Patents by Inventor Sheng-Wen Lin

Sheng-Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966133
    Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: April 23, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
  • Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Patent number: 10338760
    Abstract: A touch sensor unit includes a substrate and a plurality of touch electrodes disposed on the substrate for generating sensing signals. Each of the touch electrodes includes an electrically insulating layer that is light-transmissible, and a plurality of nano-scale conducting elements distributed in the electrically insulating layer and electrically connected to one another. Each of the conducting elements includes a metal body that has a roughened surface, that has a twisted structure, or that is formed with a light light-absorbing member thereon.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 2, 2019
    Assignee: TPK Universal Solutions Limited
    Inventors: Kuo-Feng Kao, Sheng-Wen Lin, Po-Yi Wu, Shiang-Ting Wu
  • Publication number: 20150378464
    Abstract: A touch sensor unit includes a substrate and a plurality of touch electrodes disposed on the substrate for generating sensing signals. Each of the touch electrodes includes an electrically insulating layer that is light-transmissible, and a plurality of nano-scale conducting elements distributed in the electrically insulating layer and electrically connected to one another. Each of the conducting elements includes a metal body that has a roughened surface, that has a twisted structure, or that is formed with a light light-absorbing member thereon.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 31, 2015
    Inventors: Kuo-Feng Kao, Sheng-Wen Lin, Po-Yi Wu, Shiang-Ting Wu
  • Patent number: 9189588
    Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Cheng-Lung Tsai, Sheng-Wen Lin, Kuei-Liang Lu, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20150161321
    Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Inventors: Wen-Li Cheng, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Cheng-Lung Tsai, Sheng-Wen Lin, Kuei-Liang Lu, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8751976
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 10, 2014
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8745550
    Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8739080
    Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140013287
    Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
  • Publication number: 20140007024
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8113692
    Abstract: A light source module for generating polarized light includes a light emitting element, a reflector, and an optical element. The light emitting element generates a light ray, and the reflector reflects the light ray towards the optical element. The optical element includes a light splitting face and a reflection face. The light splitting face receives the light ray, and an angle between the light splitting face and the incident light ray is at about a Brewster's Angle. After the light ray is irradiated to the light splitting face, the light ray is divided into a refraction light and a reflection light. The reflection face reflects the refraction light, and the reflection face is substantially perpendicular to a path of the refraction light. Therefore, a light source with a high degree of polarization is realized by a design of the light splitting face and the reflection face.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: February 14, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Jung-Tsung Chou, Hui-Lung Kuo, Pin-Chen Chen, Yi-Ying Lai, Sheng-Wen Lin
  • Publication number: 20110240402
    Abstract: The disclosure provides a unit with a sound isolation/vibration isolation structure, an array employing the same, and a method for fabricating the same. The unit with a sound isolation/vibration isolation structure includes: a hollow frame surrounding an inside space; a film disposed within the inside space, vertically contacting an inside wall of the hollow frame; and a body mass disposed on a top surface of the film. Particularly, the horizontal area of the inside space is larger than the area of the top surface of the film.
    Type: Application
    Filed: August 20, 2010
    Publication date: October 6, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jung-Tsung Chou, Ting-Chu Lu, Yu-Tsung Chiu, Horng-Yuan Wen, Hui-Lung Kuo, Ping-Chen Chen, Yi-Chun Liu, Wen-Liang Liu, Sheng-Wen Lin
  • Publication number: 20100142048
    Abstract: A light source module for generating polarized light includes a light emitting element, a reflector, and an optical element. The light emitting element generates a light ray, and the reflector reflects the light ray towards the optical element. The optical element includes a light splitting face and a reflection face. The light splitting face receives the light ray, and an angle between the light splitting face and the incident light ray is at about a Brewster's Angle. After the light ray is irradiated to the light splitting face, the light ray is divided into a refraction light and a reflection light. The reflection face reflects the refraction light, and the reflection face is substantially perpendicular to a path of the refraction light. Therefore, a light source with a high degree of polarization is realized by a design of the light splitting face and the reflection face.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 10, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jung-Tsung Chou, Hui-Lung Kuo, Pin-Chen Chen, Yi-Ying Lai, Sheng-Wen Lin
  • Patent number: 7619712
    Abstract: A polarizer-alignment dual function film. The film comprising an optically anisotropic material layer having a plurality of strips integrally formed thereon. The strips provide an alignment function for aligning the liquid crystal molecules while the optically anisotropic material provides a polarization function such that the two functions can be integrated into a single-layered film.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: November 17, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Ying Lai, Hui-Lung Kuo, Sheng-Wen Lin, Pin-Chen Chen, Mei-Chih Peng, Yi-Ping Hsieh
  • Publication number: 20080158499
    Abstract: A polarizer-alignment dual function film. The film comprising an optically anisotropic material layer having a plurality of strips integrally formed thereon. The strips provide an alignment function for aligning the liquid crystal molecules while the optically anisotropic material provides a polarization function such that the two functions can be integrated into a single-layered film.
    Type: Application
    Filed: September 21, 2007
    Publication date: July 3, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Ying Lai, Hui-Lung Kuo, Sheng-Wen Lin, Pin-Chen Chen, Mei-Chih Peng, Yi-Ping Hsieh
  • Publication number: 20060012059
    Abstract: A resin is spread on a transparent substrate to form a resin layer. The resin layer has a plurality of strip structures, and a viscosity of the resin is between 20 and 1000 cps. Next, the resin layer is cured such that a combination of the transparent substrate and the resin layer becomes an optical sheet.
    Type: Application
    Filed: September 14, 2004
    Publication date: January 19, 2006
    Inventors: Ya-Chuan Cheng, Sheng-Wen Lin, Tseng-Cheng Wu