Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

Abstract: A device includes a first channel region and a first gate structure formed over the first channel region. A first source/drain region is adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers. A gradient of decreasing concentration of the first dopant is one decade for every 5.5 to 7.5 nanometers deeper than the first concentration.

Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.

Abstract: A device includes a first channel region and a first gate structure formed over the first channel region. A first source/drain region is adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers. A gradient of decreasing concentration of the first dopant is one decade for every 5.5 to 7.5 nanometers deeper than the first concentration.

Abstract: An embodiment method of forming a source/drain region for a transistor includes forming a recess in a substrate, epitaxially growing a semiconductor material in the recess, amorphizing the semiconductor material, and doping the semiconductor material to form a source/drain region. In an embodiment, the doping utilizes either phosphorus or boron as the dopant. Also, the amorphizing and the doping may be performed simultaneously. The amorphizing may be performed at least in part by doping with helium.

Abstract: Methods and systems that include receiving a plurality of reflectivity measurements on a semiconductor wafer. A reflectivity map is generated based on the received plurality of reflectivity measurements. The generated reflectivity map is used to determine a process parameter of an epitaxial growth process using the reflectivity map. In an embodiment, the process parameter is a power setting (heating) of a lamp of a CVD epitaxy tool.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.

Abstract: A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer.

Abstract: Methods and systems that include receiving a plurality of reflectivity measurements on a semiconductor wafer. A reflectivity map is generated based on the received plurality of reflectivity measurements. The generated reflectivity map is used to determine a process parameter of an epitaxial growth process using the reflectivity map. In an embodiment, the process parameter is a power setting (heating) of a lamp of a CVD epitaxy tool.

Abstract: An embodiment method of forming a source/drain region for a transistor includes forming a recess in a substrate, epitaxially growing a semiconductor material in the recess, amorphizing the semiconductor material, and doping the semiconductor material to form a source/drain region. In an embodiment, the doping utilizes either phosphorus or boron as the dopant. Also, the amorphizing and the doping may be performed simultaneously. The amorphizing may be performed at least in part by doping with helium.

Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ILD layer by forming a first portion of an inter-layer dielectric (ILD) layer on a semiconductor substrate; and forming a second portion of an ILD layer on the first portion of the ILD layer. The second portion may have a greater silicon content than the first portion. For example, the second portion may be a silicon rich oxide.

Abstract: A system includes a computer-readable medium that stores a plurality of instructions for execution by at least one computer processor. The instructions include receiving a reflectivity measurement on a semiconductor wafer and generating a reflectivity map based on the received reflectivity measurement. The instructions determine a spatial distance for a selected reflectivity change using the generated reflectivity map. Subsequently, the determined spatial distance is compared with a thermal diffusion length of a first anneal process technique. In embodiments, the system further includes a light source and a reflectivity measurement tool.

Abstract: A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer.

Abstract: A system includes a computer-readable medium that stores a plurality of instructions for execution by at least one computer processor. The instructions include receiving a reflectivity measurement on a semiconductor wafer and generating a reflectivity map based on the received reflectivity measurement. The instructions determine a spatial distance for a selected reflectivity change using the generated reflectivity map. Subsequently, the determined spatial distance is compared with a thermal diffusion length of a first anneal process technique. In embodiments, the system further includes a light source and a reflectivity measurement tool.

Abstract: The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.

Abstract: The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.