Abstract: A rehabilitation device is provided, including abase, a finger sleeve assembly and a thumb sleeve assembly. The finger sleeve assembly includes a finger frame rotatably connected to the base and including first linkage slots, first linkage mechanisms disposed within the first linkage slots, and a first actuator rotatably connected to the base and a first actuator slot of the finger frame and configured to drive the finger frame so that the first linkage mechanisms are swingable with the finger frame. The thumb sleeve assembly includes a thumb frame rotatably connected to the base and including a second actuator slot, a second linkage mechanism disposed within the second actuator slot, and a second actuator rotatably connected to the base and a second actuator slot of the thumb frame and configured to drive the thumb so that the second linkage mechanism is swingable with the thumb frame.

Abstract: Methods which make use of baculovirus vector (BV)-magnetic nanoparticle (BV-MNP) complexes to facilitate in vivo delivery of clustered regularly interspaced palindromic repeat (CRISPR) systems are provided. BV-MNP complexes carrying a CRISPR nuclease and a guide RNA having homology to an immune checkpoint gene can be administered to a subject to inhibit the immune checkpoint gene. Inhibition of the immune checkpoint gene can promote a desired immune response in the subject. Methods which leverage the contrast provided by MNPs in BV-MNP complexes in combination with magnetic resonance imaging (MRI) to detect in vivo delivery of CRISPR systems are also provided.

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A silicon optical chip with integrated antenna array comprises a wavelength division multiplexer, antenna array, photodiode, amplifier, and electro-optical modulator. The wavelength division multiplexer is configured to receive an optical signal with a plurality of wavelengths and to divide the optical signal into a plurality of wavelength division optical signals, or is configured to integrate a plurality of wavelength division optical signals into optical signals to output. The antenna array is configured to receive or transmit radio frequency signals. The amplifier is signally connected to the photodiode and the antenna and is configured to amplify the radio frequency signal received by the antenna. The electro-optical modulator is signally connected to the amplifier and the wavelength division multiplexer and is configured to transform the amplified radio frequency signal into wavelength division optical signals to input to the wavelength division multiplexer.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: An information security threat determination method and an information security threat determination device are provided. The information security threat determination method and the information security threat determination device are applicable to a network system including a terminal, a core network and a server. The information security threat determination method includes the following steps: receiving information about an abnormal event occurring in the network system; performing a cause and effect tree inspection procedure to generate a plurality of tracing causes according to the abnormal event and deploying a virtual terminal and a virtual server to communicate through the core network to verify whether each tracing cause will cause the abnormal event, thereby generating inspection result; and performing decision chain procedure to determine the abnormal event as non-information security threat event or information security threat event according to the inspection result.

Abstract: Techniques for machine learning for prioritizing traffic in multi-purpose inline cloud analysis (MICA) to enhance malware detection are disclosed. In some embodiments, a system, a process, and/or a computer program product for machine learning for prioritizing traffic in multi-purpose inline cloud analysis (MICA) to enhance malware detection includes processing a set of data for network security analysis to extract a file; determining that the file is to be offloaded to a cloud security entity for security processing based at least in part on a prefilter model that is implemented as a machine learning model; forwarding the file to the cloud security entity using a multi-purpose inline cloud analysis (MICA) channel; and performing an action in response to receiving a verdict from the cloud security entity.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: The present disclosure provides a single-channel test device. The single-channel test device includes a metal flange, and a waveguide-coaxial conversion structure and a first square straight waveguide which are disposed along a central axis of the metal flange and disposed on two opposite sides of the metal flange respectively, wherein in the case that a waveguide aperture of one end of the first square straight waveguide distal to the metal flange is placed on and is kept in close contact with a single antenna unit to be tested in a phased reflectarray to be tested, the single-channel test device is configured to test a scattering parameter of the antenna unit to be tested.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: Provided are compositions comprising chemically synthesized pseudaminic acid (Pse) conjugated to a carrier protein using the OPA chemistry, methods of using said compositions to stimulate immune responses in subjects and protect the vaccinated subjects from infections caused by Pse-producing A. baumannii.

Abstract: The present invention provides a coal feeding control method and system for a small pulverized coal silo, the method includes: acquiring a boiler load increase signal, and determining the target function F(t) for boiler load control obtaining the current coal mill output signal B(t), where B(t) is the fuel quantity signal at the outlet of the coal mill that changes over time from the start time; comparing B(t) with F(t): if B(t) cannot meet the fuel quantity requirements of F(t), activate the small pulverized coal silo connected to the boiler; otherwise, the small pulverized coal silo remains inactive; determining the coal feeding signal f(t) for the small pulverized coal silo, and further determining the coal feeding control signal f(t) for the small pulverized coal silo; controlling the small pulverized coal silo to feed coal to the boiler, quickly changing the combustion rate in the furnace, and increasing the boiler load.

Abstract: The present invention belongs to the field of biopharmaceuticals and relates to an anti-DKK1 antibody, a pharmaceutical composition thereof, and use thereof. Specifically, the present invention relates to an anti-DKK1 antibody or an antigen-binding fragment thereof, wherein the anti-DKK1 antibody comprises a heavy chain variable region comprising HCDR1 to HCDR3 and a light chain variable region comprising LCDR1 to LCDR3, wherein the amino acid sequence of HCDR1 is selected from SEQ ID NO: 1, etc., the amino acid sequence of HCDR2 is selected from SEQ ID NO: 2, etc., the amino acid sequence of HCDR3 is selected from SEQ ID NO: 3, etc., the amino acid sequence of LCDR1 is selected from SEQ ID NO: 4, etc., the amino acid sequence of LCDR2 is selected from SEQ ID NO: 5, etc., and the amino acid sequence of LCDR3 is selected from SEQ ID NO: 6, etc.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.