Patents by Inventor Sheng-Yang Peng

Sheng-Yang Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9726488
    Abstract: A heading calibration method, adapted for a compass sensor is provided. The heading calibration method includes the following steps. R data segments are sequentially generated by rotating the compass sensor by a predetermined angle, wherein the data segments includes a plurality of magnetic data respectively. A partial calibration process is executed to calibrate a reference point coordinate according to the magnetic data in rth data segment and a initial value of the reference point coordinate, wherein r is between 1 and the R. Parts of the magnetic data in the rth data segment is extracted as whole data, and a whole calibration process is executed according to the whole data to update an initial value of the reference point coordinate. The partial calibration process is executed according to the updated initial value of the reference point coordinate and the magnetic data in a (r+1)th data segment.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 8, 2017
    Assignee: ITE Tech. Inc.
    Inventors: Sheng-Yang Peng, Tzu-Yi Wu
  • Publication number: 20150032399
    Abstract: A heading calibration method, adapted for a compass sensor is provided. The heading calibration method includes the following steps. R data segments are sequentially generated by rotating the compass sensor by a predetermined angle, wherein the data segments includes a plurality of magnetic data respectively. A partial calibration process is executed to calibrate a reference point coordinate according to the magnetic data in rth data segment and a initial value of the reference point coordinate, wherein r is between 1 and the R. Parts of the magnetic data in the rth data segment is extracted as whole data, and a whole calibration process is executed according to the whole data to update an initial value of the reference point coordinate. The partial calibration process is executed according to the updated initial value of the reference point coordinate and the magnetic data in a (r+1)th data segment.
    Type: Application
    Filed: January 16, 2014
    Publication date: January 29, 2015
    Applicant: ITE TECH. INC.
    Inventors: Sheng-Yang Peng, Tzu-Yi Wu
  • Publication number: 20150025657
    Abstract: An electronic device includes a first machine assembly, a second machine assembly, a first sensor, a second sensor, and a control circuit. The second machine assembly is pivoted to the first machine assembly. The first sensor is located on the first machine assembly and configured to generate first sensing data when the electronic device is in a non-normal working state. The second sensor is located on the second machine assembly and configured to generate second sensing data when the electronic device is in the non-normal working state. The control circuit is coupled to the first sensor and the second sensor and configured to perform a first default operation according to the first sensing data and the second sensing data.
    Type: Application
    Filed: October 31, 2013
    Publication date: January 22, 2015
    Applicant: ITE TECH. INC.
    Inventors: Sheng-Yang Peng, Lee-Chun Guo
  • Publication number: 20130292803
    Abstract: A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.
    Type: Application
    Filed: July 1, 2013
    Publication date: November 7, 2013
    Inventor: Sheng-Yang Peng
  • Patent number: 8501579
    Abstract: A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: August 6, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Sheng-Yang Peng
  • Publication number: 20130161670
    Abstract: Light emitting, diode (LED) packages and processes with improved heat dissipation. In certain embodiments, only metal solder resides in the space between the leadframe and the circuit board, providing good heat conduction from the LED chip to the circuit board. In certain embodiments, sidewalls of the leadframe are tilted to provide improved light emission.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventor: Sheng-Yang Peng
  • Publication number: 20100230788
    Abstract: A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.
    Type: Application
    Filed: February 10, 2010
    Publication date: September 16, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: SHENG-YANG PENG
  • Patent number: 7611967
    Abstract: A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of the carrier is greater than the dimension of the wafer. Next, the surface of the wafer is bonded to the carrier, and the strip-shaped adhesives or the fiducial mark is extended or located outside a bonding region between the wafer and the carrier. Here, the surface of the wafer faces the carrier. The cutting tool and the carrier are positioned according to the strip-shaped adhesives or the fiducial mark outside the bonding region. The wafer is then sawed by using the cutting tool. The wafer sawing method provides a precise and rapid sawing process and achieves superior productive yield.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: November 3, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Sheng-Yang Peng
  • Patent number: 7573124
    Abstract: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: August 11, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Jen Wang, Kuo-Pin Yang, Wei-Min Hsiao, Sheng-Yang Peng
  • Publication number: 20090140413
    Abstract: A semiconductor package structure and the applications thereof and the manufacturing method are disclosed. The semiconductor package structure includes a carrier, a semiconductor device, a first package body, a lid and a second package body. The semiconductor device is electrically connected to the carrier via a first conductive element. The first package body is molded on the carrier to surround the semiconductor device. The lid is disposed on top of the first package body and has at least one protrusion. The second package body is molded on the carrier to encapsulate the protrusion, whereby the protrusion is embedded within the second package body thereby locking the lid in place against the first package body.
    Type: Application
    Filed: June 12, 2008
    Publication date: June 4, 2009
    Inventors: Meng-Jen WANG, Kuo-Pin Yang, Sheng-Yang Peng, Wei-Min Hsiao
  • Publication number: 20080261351
    Abstract: A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of the carrier is greater than the dimension of the wafer. Next, the surface of the wafer is bonded to the carrier, and the strip-shaped adhesives or the fiducial mark is extended or located outside a bonding region between the wafer and the carrier. Here, the surface of the wafer faces the carrier. The cutting tool and the carrier are positioned according to the strip-shaped adhesives or the fiducial mark outside the bonding region. The wafer is then sawed by using the cutting tool. The wafer sawing method provides a precise and rapid sawing process and achieves superior productive yield.
    Type: Application
    Filed: March 12, 2008
    Publication date: October 23, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Sheng-Yang Peng
  • Publication number: 20080230885
    Abstract: A chip hermetic package device includes a substrate, a chip, a hermetic lid, a hermetic material and a post. The height of the post is larger than the thickness of the hermetic material. A method for producing a chip hermetic package includes the steps of: mounting the chip on the substrate; disposing the post and the hermetic material between the substrate and the hermetic lid; disposing the hermetic lid on the substrate to form a chamber, the post supporting the hermetic lid on the substrate to form an air passage; and performing a sealing step in an atmosphere of inert gas. The present invention utilizes the post to form the air passage between the substrate and the hermetic lid. Therefore, only is the sealing step performed in the atmosphere of nitrogen, and present invention needs a reduced number of equipment. Therefore, the present invention has a low cost, simplifies the packaging process and improves efficiency.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-jen Wang, Kuo-pin Yang, Sheng-yang Peng
  • Publication number: 20080087987
    Abstract: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.
    Type: Application
    Filed: July 2, 2007
    Publication date: April 17, 2008
    Inventors: Meng-Jen Wang, Kuo-Pin Yang, Wei-Min Hsiao, Sheng-Yang Peng
  • Publication number: 20070252261
    Abstract: The present invention relates to a semiconductor device package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of conductive elements, a pre-mold and a lid. The first semiconductor device is electrically connected to the carrier. The second semiconductor device is disposed above the first semiconductor device. The conductive elements are used for electrically connecting the second semiconductor device and the carrier. The pre-mold and the carrier form an accommodating space for accommodating the first semiconductor device, the second semiconductor device and the conductive elements. The lid is adhered to the pre-mold for covering the opening of the pre-mold. As a result, the pre-mold is formed by molding, the manufacture process of the present invention is simpler than that of the conventional semiconductor device package.
    Type: Application
    Filed: December 18, 2006
    Publication date: November 1, 2007
    Inventors: Meng-Jen Wang, Kuo-Pin Yang, Sheng-Yang Peng, Wei-Min Hsiao
  • Patent number: 7071553
    Abstract: The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: July 4, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh Tsai, Sheng-Yang Peng
  • Publication number: 20050006756
    Abstract: The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.
    Type: Application
    Filed: September 3, 2004
    Publication date: January 13, 2005
    Inventors: Tsung-Yueh Tsai, Sheng-Yang Peng
  • Patent number: 6801429
    Abstract: The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: October 5, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh Tsai, Sheng-Yang Peng
  • Publication number: 20040165351
    Abstract: The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.
    Type: Application
    Filed: September 8, 2003
    Publication date: August 26, 2004
    Inventors: TSUNG-YUEH TSAI, SHENG-YANG PENG
  • Patent number: D919635
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: May 18, 2021
    Assignee: CyCraft Singapore Pte. Ltd.
    Inventors: Ming-Chang Chiu, Sheng-Yang Peng, Pei Kan Tsung, Ming Wei Wu
  • Patent number: D922402
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 15, 2021
    Assignee: CYCARRIER TECHNOLOGY CO., LTD.
    Inventors: Ming-Chang Chiu, Sheng-Yang Peng, Pei Kan Tsung, Ming Wei Wu