Patents by Inventor Sheng Yen

Sheng Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250066899
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
  • Patent number: 12219880
    Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Publication number: 20250031472
    Abstract: Embodiments of the present disclosure relate to a structure, which includes a plurality of photodiode doping regions formed in a substrate, and a deep trench isolation (DTI) structure formed in the substrate, wherein the DTI structure separates photodiode doping regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material includes a top, a sidewall, and a bottom. The structure also includes a first isolation layer surrounding and in contact with the top, the sidewall, and the bottom of the first filling material.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Sheng Chieh CHUANG, Shu Yen KUNG, Tsun-Kai TSAO, Ming Chyi LIU
  • Publication number: 20250003999
    Abstract: The present disclosure provides an automated system and a method for isolation and/or extracting substance by magnetic beads. With the preset program, sample isolation and the following assay such as PCR or Immunoprecipitation may be performed in single instrument of automated system.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 2, 2025
    Applicant: TAIWAN ADVANCED NANOTECH INC.
    Inventors: CHIEN-HSING CHIEN, JUNG-HSIEN HUNG, KAN-SANG MOK, SHENG-YEN HUANG
  • Publication number: 20240420455
    Abstract: Techniques regarding generating a synthetic dataset of objects are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a defining component that can define a tractable forward process associated with a diffusion model, with defining the tractable forward process including inputting noise to compromise training data, resulting in compromised training data. The computer executable components can further include a training component that, using the compromised training data, trains the diffusion model to reverse process the tractable forward process, wherein the training results in a compromised diffusion model.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 19, 2024
    Inventors: Pin-Yu Chen, I-Hsin Chung, Bo Wu, Chuang Gan, Tsung-Yi Ho, Sheng-Yen Chou
  • Patent number: 12113544
    Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 8, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Sheng-Yen Shih, Shih-Hsiung Huang, Wei-Cian Hong
  • Patent number: 12107597
    Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: October 1, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Wei-Cian Hong, Sheng-Yen Shih
  • Publication number: 20240319904
    Abstract: A method of managing access to a first memory via a second memory includes autonomously copying data from one or more of the data blocks in the first plurality of data blocks in the first memory to corresponding one or more of the data blocks in the second plurality of data blocks in the second memory sequentially. Access to the first memory with a first plurality of data blocks is at a first speed and access to the second memory with a second plurality of data blocks is at a second speed. A command is received for reading from the second memory. Responsive to receiving the command, a pointer is obtained indicating an address of a data block in the second memory that contains data copied from the first memory and that is first available for access. The data is obtained from the data block based on the pointer.
    Type: Application
    Filed: January 9, 2024
    Publication date: September 26, 2024
    Applicant: MediaTek Inc.
    Inventors: Pao-Hung Kuo, Po-Chun Fan, Sheng-Yen Yang
  • Publication number: 20240320706
    Abstract: A terminal includes one or more processors, and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: displaying an analysis screen of a livestream associated with a selling item on a display; and displaying, on the analysis screen, a first object indicating a sales activity on a livestreamer side and a second object indicating reactions on viewers side together along a same time axis.
    Type: Application
    Filed: October 16, 2023
    Publication date: September 26, 2024
    Inventors: Hao-Jung LO, Chia-Yi YANG, Yu-Hsin CHIANG, Cheng-Chieh CHANG, Sheng-Yen WANG, Liang-Fang TSAI
  • Patent number: 12068755
    Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 20, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Wei-Cian Hong, Sheng-Yen Shih
  • Publication number: 20240242661
    Abstract: A display device includes first and second pixel circuits, first and second gate lines, and first and second transmission lines. The first pixel circuit emits light according to a data signal, and is charged according to a first gate signal. The second pixel circuit emits light according to the data signal, and is charged according to a second gate signal. The first gate line is located between the first second pixel circuits, and provides the first gate signal. The second gate line provides the second gate signal. The first transmission line provides the second gate signal to the second gate line. The second transmission line is located between the first transmission line and the second pixel circuit, crosses over the second gate line, and provides the first gate signal to the first gate line.
    Type: Application
    Filed: July 7, 2023
    Publication date: July 18, 2024
    Inventors: Yueh-Chi WU, Shu-Wen LIAO, Ti-Kuei YU, Ya-Ling HSU, Sheng-Yen CHENG, Yueh-Hung CHUNG
  • Patent number: 12029007
    Abstract: A cooling system and a cooling device are provided. The cooling device includes a container, a heat dissipation module, and a cooling module. The cooling module includes a cover plate and a heat dissipation fin assembly. The cover plate covers an opening of the container. The cover plate includes a cooling channel. The cooling channel is arranged in the cover plate and includes an inlet and an outlet. The inlet and the outlet are respectively located at two sides of the cover plate. One side of the heat dissipation fin assembly is in contact with a surface of the cover plate, and an other side of the heat dissipation fin assembly is located in the container. Through the above structure, a usage amount of heat transfer fluid injected into the container of the cooling device is lower than that of a conventional immersion cooling device.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: July 2, 2024
    Assignee: WISTRON CORPORATION
    Inventors: Hua Chen, Sheng-Yen Lin, Chuan-Yi Liang
  • Patent number: 12027108
    Abstract: A display device includes first and second pixel circuits, first and second gate lines, and first and second transmission lines. The first pixel circuit emits light according to a data signal, and is charged according to a first gate signal. The second pixel circuit emits light according to the data signal, and is charged according to a second gate signal. The first gate line is located between the first second pixel circuits, and provides the first gate signal. The second gate line provides the second gate signal. The first transmission line provides the second gate signal to the second gate line. The second transmission line is located between the first transmission line and the second pixel circuit, crosses over the second gate line, and provides the first gate signal to the first gate line.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: July 2, 2024
    Assignee: AUO CORPORATION
    Inventors: Yueh-Chi Wu, Shu-Wen Liao, Ti-Kuei Yu, Ya-Ling Hsu, Sheng-Yen Cheng, Yueh-Hung Chung
  • Publication number: 20240213999
    Abstract: A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 27, 2024
    Inventors: YAN-HUI WU, Yao-Ming Lu, Tai-Cheng Lee, Chih-Lung Chen, Sheng-Yen Shih
  • Publication number: 20240083828
    Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.
    Type: Application
    Filed: June 28, 2023
    Publication date: March 14, 2024
    Inventors: Wen-Hsi HUANG, Sheng-Yen KO, Shih-Hong CHEN, Chun-Yu LIN
  • Publication number: 20240047435
    Abstract: A luminous panel includes a circuit board, a plurality of connecting pads, a chip and two alignment structures. The connecting pads are located on the circuit board. The chip is located on the circuit board and at least partially covers the connecting pads. The two alignment structures are located on the circuit board. The two alignment structures and the connecting pads are at the same level. The two alignment structures are located at two diagonal corners of the chip. At least one part of the two alignment structures protrudes from the outline of the chip.
    Type: Application
    Filed: December 27, 2022
    Publication date: February 8, 2024
    Inventors: Tzu-Chun LIN, Sheng-Yen CHENG, Jia-Hong WANG, Yueh-Hung CHUNG, Ya-Ling HSU, Chen-Hsien LIAO
  • Publication number: 20240017525
    Abstract: A resin composition and a metal clad substrate are provided. The resin composition includes: 20 phr to 40 phr of an epoxy resin, 40 phr to 60 phr of a modified benzoxazine resin, 2 phr to 10 phr of a maleimide resin, and 25 phr to 50 phr of fillers. The modified benzoxazine resin contains a DOPO group. Based on a total weight of the modified benzoxazine resin being 100 wt %, an amount of the DOPO group ranges from 10 wt % to 20 wt %.
    Type: Application
    Filed: December 25, 2022
    Publication date: January 18, 2024
    Inventors: SHENG-YEN WU, KAI-YANG CHEN, MENG-HAN YEH, LI-CHUNG LU
  • Patent number: 11876103
    Abstract: A display panel includes a plurality of sub-pixel structures and a plurality of transfer elements. The sub-pixel structures include a plurality of first sub-pixel structures. A data line of each of the first sub-pixel structures is disposed adjacent to a corresponding transfer element, and a scan line of each of the first sub-pixel structures is electrically connected to the corresponding transfer element. The first sub-pixel structures include a plurality of first-type sub-pixel structures and a plurality of second-type sub-pixel structures. When the display panel displays a grayscale picture, each of the first-type sub-pixel structures has first brightness, each of the second-type sub-pixel structures has second brightness. The first brightness is less than the second brightness. A total number of the first sub-pixel structures of the display panel is A, a number of the first-type sub-pixel structures in the first sub-pixel structures is a, and 50%<(a/A)<100%.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: January 16, 2024
    Assignee: AUO Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11876526
    Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Kai-Yue Lin, Wei-Jyun Wang, Sheng-Yen Shih
  • Publication number: 20240002653
    Abstract: A resin composition and a metal clad substrate are provided. The resin composition includes: 5 phr to 15 phr of a maleimide resin, 5 phr to 30 phr of a benzoxazine resin, 40 phr to 70 phr of an epoxy resin, and 40 phr to 60 phr of fillers. An amount of fluorine atoms contained in the maleimide resin ranges from 10 wt % to 50 wt %.
    Type: Application
    Filed: May 8, 2023
    Publication date: January 4, 2024
    Inventors: SHENG-YEN WU, SHOU-NENG TO, YA-PING LIU, CHEN-HAO CHANG, PEI-CHUN LAI