Abstract: A manufacturing method for the inductor/transformer is disclosed. A simulator is used to simulate the inductance, the quality factor, and the self-resonance frequency of said inductor/transformer to generate at least one group of the area size, the number of the conductive layer, the line width, the number of turns, and/or the line space of the conductive layers and the first conductive layer; the inductor/transformer is manufactured according to the factors. Thereafter, the Monte-Carlo simulation is used to initiate the process variability analysis of the factors of the conductive layer and the first conductive layer, and the geometric size of the inductor/transformer can be modulated according to the results of the process variability analysis during the manufacturing process, such that the inductor/transformer can be manufactured by the process of the generic logic circuit.

Abstract: A semiconductor device including a substrate of a first semiconductor type with a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

Abstract: A model modification method for a semiconductor device comprises the steps of: analyzing the electrical properties of a goal semiconductor device, in detail, to build a goal model that can be used to describe the behavior of the goal semiconductor device; and modifying the goal model according to the results of the WAT to obtain a modified model that can be used accurately to describe the behavior of produced semiconductor devices.

Abstract: A method for analyzing circuit comprises the steps of selecting a plurality of elements; sampling the selected elements, resulting in a plurality of sampling-parameter sets; simulating the sampling-parameter sets to generate a plurality of simulation-results, and process the regression operation for the sampling-parameter sets and simulation-results in order to acquire the contribution rank of each sampling-parameter set and element. Accordingly, while analyzing similar circuits, the partial elements can be selected according to the contribution rank and further sampled; thereby, the amount of sampling-parameter sets can be advantageously reduced, and the analysis efficiency can be improved according to the circuit.

Abstract: A manufacturing method for the inductor/transformer is disclosed. A simulator is used to simulate the inductance, the quality factor, and the self-resonance frequency of said inductor/transformer to generate at least one group of the area size, the number of the conductive layer, the line width, the number of turns, and/or the line space of the conductive layers and the first conductive layer; the inductor/transformer is manufactured according to the factors. Thereafter, the Monte-Carlo simulation is used to initiate the process variability analysis of the factors of the conductive layer and the first conductive layer, and the geometric size of the inductor/transformer can be modulated according to the results of the process variability analysis during the manufacturing process, such that the inductor/transformer can be manufactured by the process of the generic logic circuit.

Abstract: A semiconductor device including a substrate of a first semiconductor type with a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

Abstract: A semiconductor device. The device includes a substrate of the first semiconductor type comprising a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

Abstract: An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate and surrounds the circuit and the I/O pad. The ground ring is formed between the silicon substrate and the I/O pad, and the ground ring is electrically connected with the seal ring. The guard ring is formed above the silicon substrate and surrounds the I/O pad, and the guard ring is electrically connected with the seal ring.

Abstract: An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate and surrounds the circuit and the I/O pad. The ground ring is formed between the silicon substrate and the I/O pad, and the ground ring is electrically connected with the seal ring. The guard ring is formed above the silicon substrate and surrounds the I/O pad, and the guard ring is electrically connected with the seal ring.

Abstract: An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate and surrounds the circuit and the I/O pad. The ground ring is formed between the silicon substrate and the I/O pad, and the ground ring is electrically connected with the seal ring. The guard ring is formed above the silicon substrate and surrounds the I/O pad, and the guard ring is electrically connected with the seal ring.

Abstract: A method for circuit design support. A netlist file is received. A first 4-terminal device is acquired from the netlist. A second 4-terminal device with the same specifications as the first 4-terminal device is acquired. A first determination is performed to determine whether all control terminals of the first device and all control terminals of the second device are untied-up. A second determination is performed to determine whether all conduction terminals of the first device and all conduction terminals of the second device are tied-up. A relationship indicating that the first 4-terminal device and the second 4-terminal device are a differential pair is output if the first and second determinations are reached.

Abstract: A method for circuit simulation. Manufacturing parameters, geometry data and status case types are acquired, and provided to an extreme mismatch model. The extreme mismatch model comprises at least one simulation instruction simulating electrical features under the manufacturing parameters, geometry data and status case types. An extreme electrical feature is acquired by performing normal simulation employing the extreme mismatch model. The extreme electrical feature is outputted.

Abstract: A semiconductor device. The device includes a substrate of the first semiconductor type comprising a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

Abstract: A method for circuit design support. A device instance identity is acquired. A device specification screen comprising at least one input field for entering at least one manufacturing parameter corresponding to the device instance identity is displayed. At least one target electrical characteristic variation is determined by applying the manufacturing parameter, a maximum extreme case and a minimum extreme case to a simulation model. The target electrical characteristic variation is displayed on the device specification screen.

Abstract: An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate and surrounds the circuit and the I/O pad. The ground ring is formed between the silicon substrate and the I/O pad, and the ground ring is electrically connected with the seal ring. The guard ring is formed above the silicon substrate and surrounds the I/O pad, and the guard ring is electrically connected with the seal ring.