Patents by Inventor Sheng-Yu Chang
Sheng-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955535Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.Type: GrantFiled: July 26, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240114698Abstract: A semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. The bottom electrode is over the substrate. The ferroelectric layer is over the bottom electrode. The noble metal electrode is over the ferroelectric layer. The non-noble metal electrode is over the noble metal electrode.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yu CHEN, Sheng-Hung SHIH, Fu-Chen CHANG, Kuo-Chi TU, Wen-Ting CHU, Alexander KALNITSKY
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Publication number: 20240074206Abstract: A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.Type: ApplicationFiled: November 3, 2023Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Chen CHANG, Kuo-Chi TU, Tzu-Yu CHEN, Sheng-Hung SHIH
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Patent number: 10692983Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.Type: GrantFiled: March 28, 2019Date of Patent: June 23, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting Li, Chih-Hao Chang, Sheng-Yu Chang, Jen-Hsiang Lu, Jyun-Yang Shen
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Patent number: 10379875Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a first storage zone and a second storage zone. A boot code loader is stored in the first storage zone. The non-volatile memory includes a memory cell array. The memory cell array includes a third storage zone and a fourth storage zone. A specified program is stored in the third storage zone. The third storage zone contains a first block. A first page of the first block is divided into a first portion and a second portion. A first binary code of the specified program is repeatedly stored in plural bytes of the first portion of the first page. The one's complement of the first binary code is repeatedly stored in plural bytes of the second portion of the first page.Type: GrantFiled: January 16, 2018Date of Patent: August 13, 2019Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATIONInventors: Ping-Jie Chen, Sheng-Yu Chang, Chien-Chih Weng
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Publication number: 20190229197Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.Type: ApplicationFiled: March 28, 2019Publication date: July 25, 2019Inventors: Chung-Ting LI, Chih-Hao CHANG, Sheng-Yu CHANG, Jen-Hsiang LU, Jyun-Yang SHEN
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Publication number: 20190196955Abstract: A solid state drive is connected with a host. The solid state drive includes a non-volatile memory and a first flash translation layer. The non-volatile memory includes a first storage zone and a second storage zone. The first storage zone includes a boot area. An operating system is stored in the boot area. The first flash translation layer receives a first command and a first logical block address from the host. The first flash translation layer converts the first logical block address into a first physical block address, and the solid state drive accesses the first storage zone according to the first physical block address. The solid state drive receives a second command and a second physical block address from the host, and the solid state drive accesses the second storage zone according to the second physical block address.Type: ApplicationFiled: January 25, 2018Publication date: June 27, 2019Inventors: Sheng-Yu CHANG, Ping-Jie CHEN, Chien-Chih WENG
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Publication number: 20190155612Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a first storage zone and a second storage zone. A boot code loader is stored in the first storage zone. The non-volatile memory includes a memory cell array. The memory cell array includes a third storage zone and a fourth storage zone. A specified program is stored in the third storage zone. The third storage zone contains a first block. A first page of the first block is divided into a first portion and a second portion. A first binary code of the specified program is repeatedly stored in plural bytes of the first portion of the first page. The one's complement of the first binary code is repeatedly stored in plural bytes of the second portion of the first page.Type: ApplicationFiled: January 16, 2018Publication date: May 23, 2019Inventors: Ping-Jie CHEN, Sheng-Yu Chang, Chien-Chih Weng
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Patent number: 10269907Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.Type: GrantFiled: March 12, 2018Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting Li, Chih-Hao Chang, Sheng-Yu Chang, Jen-Hsiang Lu, Jyun-Yang Shen
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Publication number: 20180204922Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.Type: ApplicationFiled: March 12, 2018Publication date: July 19, 2018Inventors: Chung-Ting LI, Chih-Hao CHANG, Sheng-Yu CHANG, Jen-Hsiang LU, Jyun-Yang SHEN
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Patent number: 9947756Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.Type: GrantFiled: April 13, 2016Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting Li, Chih-Hao Chang, Sheng-Yu Chang, Jen-Hsiang Lu, Jyun-Yang Shen
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Publication number: 20170243944Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.Type: ApplicationFiled: April 13, 2016Publication date: August 24, 2017Inventors: Chung-Ting LI, Chih-Hao CHANG, Sheng-Yu CHANG, Jen-Hsiang LU, Jyun-Yang SHEN
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Patent number: 8932936Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.Type: GrantFiled: April 17, 2012Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chih-Hsiung Peng, Chi-Kang Chang, Chiang Mu-Chi, Sheng-Yu Chang, Hua Feng Chen, Chao-Cheng Chen, Ryan Chia-Jen Chen
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Publication number: 20130273711Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.Type: ApplicationFiled: April 17, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chih-Hsiung Peng, Chi-Kang Chang, Chiang Mu-Chi, Sheng-Yu Chang, Hua Feng Chen, Chao-Cheng Chen, Ryan Chia-Jen Chen
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Publication number: 20070067793Abstract: A portable storage device includes a plug-and-play medium for connecting with a digital set-top box, a digital key for access a TV broadcasting system via the digital set-top box so as to obtain TV performance; and a recording unit for storing files or content concerning the TV performance.Type: ApplicationFiled: September 16, 2005Publication date: March 22, 2007Inventors: Hon-Wai NG, Sheng-Yu Chang
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Publication number: 20070011225Abstract: A multimedia player is disclosed. The multimedia player comprises a host end and a receiving end. The host end comprises a transmission interface, a wireless transmission interface and a host connected to the transmission interface and the wireless transmission interface. The transmission interface is adopted for connecting to the Internet for downloading and transmitting a multimedia entertainment content. The receiving end comprises a microcontroller connected to a wireless transmission interface adopted for receiving the multimedia entertainment content transmitted from the wireless transmission interface of the host end, and a digital/analog converter for converting the multimedia entertainment content into a playable format for a playing device. The microcontroller and the digital/analog converter are connected to a monitor and said playing device respectively.Type: ApplicationFiled: July 7, 2005Publication date: January 11, 2007Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Jen Hsu, Sheng-Yu Chang