Abstract: A power supply system includes a primary side circuit, a secondary side circuit, an auxiliary winding, a blocking module, a control module, and a controller. The auxiliary winding is magnetically coupled to the secondary side winding and includes a first sub winding and a second sub winding in series. The auxiliary winding has a first tap at the dotted end of the first sub winding, a second tap at the dotted end of the second sub winding, and a ground tap coupling the second sub winding to the ground. The blocking module receives a first auxiliary voltage and a second auxiliary voltage and outputs a selected voltage. The control module controls the blocking module according to the second auxiliary voltage to output the first auxiliary voltage or the second auxiliary voltage as the selected voltage. The controller is electrically coupled to the blocking module and the control module.

Abstract: A display panel and a pixel circuit of the display panel are provided. The pixel circuit includes a driving transistor and a light-emitting time length modulator. The driving transistor has a control terminal receiving a pulse width control signal and an amplitude control signal, and the driving transistor generates a driving signal. In a first time period, the light-emitting time length modulator modulates a time length of a plurality of second time periods for providing the driving signal to a light-emitting device according to a light-emitting time control signal.

Abstract: A display panel and a pixel circuit of the display panel are provided. The pixel circuit includes a driving transistor and a light-emitting time length modulator. The driving transistor has a control terminal receiving a pulse width control signal and an amplitude control signal, and the driving transistor generates a driving signal. In a first time period, the light-emitting time length modulator modulates a time length of a plurality of second time periods for providing the driving signal to a light-emitting device according to a light-emitting time control signal.

Abstract: A display device includes a substrate, display units, and a plurality of integrated circuits (ICs). The substrate includes an active area and a non-active area. The non-active area is located around the active area. The display units are disposed in the active area of the substrate, and arranged in a matrix. The ICs are disposed in the active area of the substrate, arranged in a matrix, and are electrically coupled to the display units. Each of the ICs includes a shift register unit. Each of the shift register units of the ICs is configured to receive a previous-stage scan signal, and generate a current-stage scan signal according to the previous-stage scan signal. The ICs drive the display units according to the current-stage scan signals.

Abstract: A display device includes a substrate, display units, and a plurality of integrated circuits (ICs). The substrate includes an active area and a non-active area. The non-active area is located around the active area. The display units are disposed in the active area of the substrate, and arranged in a matrix. The ICs are disposed in the active area of the substrate, arranged in a matrix, and are electrically coupled to the display units. Each of the ICs includes a shift register unit. Each of the shift register units of the ICs is configured to receive a previous-stage scan signal, and generate a current-stage scan signal according to the previous-stage scan signal. The ICs drive the display units according to the current-stage scan signals.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory device.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory device.