Abstract: This disclosure discloses a method and apparatus for determining a quantum circuit. The method may include sampling an initial circuit unit pool according to an initial sampling manner to obtain initial K groups of circuit units and constructing and generating initial K candidate quantum circuits. The method may further include determining a performance evaluation index corresponding to the initial K candidate quantum circuits and updating the initial sampling manner and a circuit unit in the initial circuit unit pool based on the performance evaluation index, to obtain an updated sampling manner and an updated circuit unit pool. The method may further include sampling the updated circuit unit pool according to the updated sampling manner to obtain updated K groups of circuit units and constructing and generating updated K candidate quantum circuits. The method may further include determining a target quantum circuit from the updated K candidate quantum circuits.

Abstract: A qubit mapping method is performed by a computer device. The method includes: obtaining a coupling graph corresponding to a quantum device, each vertex in the coupling graph representing one qubit in the quantum device, an edge between two vertexes representing that a two-qubit gate is allowed to directly act on qubits corresponding to the two vertexes; generating at least two connected subgraphs based on the coupling graph, a quantity of vertexes of each connected subgraph being greater than or equal to 2 and less than or equal to a routing number of the coupling graph, and a sum of quantities of vertexes of the at least two connected subgraphs being equal to a constant multiple of a quantity of vertexes of the coupling graph; and performing qubit mapping on a logic circuit based on the at least two connected subgraphs, to obtain a corresponding hardware compilable circuit.

Abstract: Embodiments of this application disclose a method for designing component arrangement on a chip layout performed by a computer device. The method includes: obtaining a chip layout; determining a genus region corresponding to a first component on the chip layout based on a first arrangement parameter of the first component on the chip layout, and the genus region being a hollow region located in the first component on the chip layout; and arranging a second component in a region other than the genus region on the chip layout based on a second arrangement parameter of the second component when the genus region does not support arrangement of the second component.

Abstract: Embodiments of the present disclosure provide a method for virtualizing a quantum hardware resource performed by an electronic device. The method includes: obtaining a target qubit cell topology for a target quantum computing task; obtaining a qubit cell network in a quantum hardware resource; obtaining, from the qubit cell network, a plurality of candidate qubit cell subnetworks conforming to the target qubit cell topology; determining an overall operation fidelity of each of the candidate qubit cell subnetworks based on a self-operation fidelity of each qubit cell in the candidate qubit cell subnetwork and a mutual operation fidelity between adjacent qubit cells; and determining a target qubit cell subnetwork as a virtualized resource for the target quantum computing task based on the overall operation fidelity. According to the embodiments of the present disclosure, a utilization rate of the virtualized resource is improved, and a relatively high operation accuracy is further ensured.

Abstract: This application relates to quantum chemistry. The method includes: obtaining training data for a molecular generative model; predicting, if a labeled property value in molecular property label data of a sample molecule in the training data for at least one of M properties is missing, a property value of the sample molecule for at least one property, to obtain molecular property prediction data of the sample molecule; obtaining molecular property tag data of the sample molecule based on the molecular property label data and the molecular property prediction data of the sample molecule; and training the molecular generative model based on the molecular property tag data of the sample molecule, to obtain a trained molecular generative model. This application supports training of the molecular generative model by using the training data without the labeled property value, molecular properties are more abundant and diversity of molecular data is improved.

Abstract: A method for determining a parameter of a layout quality detection tool performed by an electronic device. The method includes: performing a quality detection on an original chip layout by using a layout quality detection tool to obtain quality indicators corresponding to first base values; when the quality indicators do not meet a reference condition, determining a first reference value from a plurality of first candidate values based on the quality indicators, and determining a plurality of second base values based on the plurality of first base values and the first reference value; performing a quality detection on the original chip layout by using the tool to obtain quality indicators corresponding to the second base values; and when the quality indicators meet the reference condition, determining a target value of the target parameter based on the second base values for improving the accuracy of the tool.

Abstract: This application provides a mask generation model training method performed by a computer device, the method including: obtaining a predicted mask of a target layout of a chip sample; inputting the predicted mask into a photolithography physical model to obtain a wafer pattern corresponding to the predicted mask; determining complexity of the predicted mask of the target layout based on a sum of perimeters of a plurality of patterns included in the target layout of the chip sample and a perimeter of the predicted mask of the target layout; and adjusting a parameter of the mask generation model based on the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout to obtain a trained mask generation model.

Abstract: A quantum task execution method is performed by a computer device. The method includes: obtaining a logical quantum circuit configured to execute a quantum task; generating a virtual quantum circuit of the quantum task according to topology information represented by a virtual quantum chip and the logical quantum circuit, the virtual quantum chip corresponding to a partial structure in a physical quantum chip, the topology information being configured for representing a topology relationship between virtual qubits included in the virtual quantum chip; generating a physical quantum circuit in the physical quantum chip for the quantum task according to the virtual quantum circuit and a bit mapping relationship between the virtual quantum chip and the physical quantum chip; and executing the physical quantum circuit through the partial structure in the physical quantum chip, to obtain an execution result of the quantum task.

Abstract: This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module.

Abstract: This application discloses methods and devices for a quantum chip, a quantum processor and a quantum computer, and relates to the field of quantum technology. The quantum chip includes a bottom sheet and a top sheet; a qubit array disposed on the top sheet, the qubit array comprising a plurality of qubits distributed in an array structure of M rows by N columns, and M and N being both integers greater than 1; a reading cavity disposed on the bottom sheet, and the reading cavity being configured to acquire status information of a qubit in the qubit array; and the bottom sheet and the top sheet being electrically connected.

Abstract: A method for processing a frequency control signal includes providing a square wave pulse to a target qubit, and controlling, after a first time elapses from an end time of the square wave pulse, the target qubit to rotate around a Y axis by a first target distance. The first time has a value that is variable. The method includes performing, after a second time elapses from the first time, a QST measurement on the target qubit and reconstructing a density matrix of the target qubit based on the QST measurement to obtain a phase parameter value of the target qubit associated with the value of the first time. Further, the method includes varying the first time and repeating the QST measurement in response to values of the first time to obtain phase parameter values associated with the values of the first time; and adjusting the frequency control signal accordingly.

Abstract: In a method for determining a superconducting impedance matched parametric amplifier, a center wavelength parameter, a gain parameter, and a bandwidth parameter of the superconducting impedance matched parametric amplifier are determined. An impedance value of an impedance matching line of the superconducting impedance matched parametric amplifier and a capacitance value of the amplifier are determined based on the wavelength parameter, the gain parameter, and the bandwidth parameter. A line width dimension of a coplanar waveguide of the superconducting impedance matched parametric amplifier is calculated based on the impedance value of the impedance matching line. A stub dimension of the superconducting impedance matched parametric amplifier is calculated based on the impedance value of the impedance matching line and the capacitance value of the amplifier.

Abstract: An airbridge arrangement method for a chip layout includes obtaining location information of n points defining routing of a coplanar waveguide (CPW) to be arranged in the chip layout, n being an integer greater than 1. The method further includes automatically determining a skeleton line of the CPW according to the location information of the n points and according to the chip layout, the skeleton line of the CPW being a center line of a center conductor of the CPW. The method further includes automatically arranging airbridges on the chip layout according to the skeleton line of the CPW.

Abstract: A superconducting quantum hybrid system includes: a silicon carbide (SiC) epitaxial layer; and a superconducting qubit line, the superconducting qubit line corresponding to a superconducting qubit, where a designated region of the SiC epitaxial layer includes a nitrogen vacancy (NV) center, the NV center being formed by implanting nitrogen ions into the designated region of the SiC epitaxial layer, and where the superconducting qubit line is located on a surface of the SiC epitaxial layer, the superconducting qubit is coupled to a solid-state defect qubit, and the solid-state defect qubit is a qubit corresponding to the NV center in the designated region.

Abstract: This disclosure describes a quantum noise process analysis method, device, and storage medium, in the field of quantum processing technologies. The method may include performing quantum process tomography (QPT) on a quantum noise process of a target quantum system, to obtain dynamical maps of the quantum noise process, wherein the QPT involves at least one measurement of the target quantum. The method further includes extracting transfer tensor maps (TTMs) of the quantum noise process from the dynamical maps; and analyzing the quantum noise process according to the TTMs. The TTM is used for representing a dynamical evolution of the quantum noise process to reflect the law of evolution of the dynamical maps of the quantum noise process over time.

Abstract: This application relates to a sideband suppression method performed at a computer device.

Abstract: A method includes determining a plurality of neural network models each corresponding to one of a plurality of molecular representations, and, for each molecular representation in the plurality of molecular representations, determining, using the neural network model corresponding to the molecular representation, a molecular property prediction result and prediction confidence corresponding to unlabeled data in an unlabeled data set, obtaining at least a portion of the unlabeled data as reference unlabeled data, the reference unlabeled data having corresponding prediction confidence higher than a preset threshold, and determining, based on the reference unlabeled data and a molecular property prediction result corresponding to the reference unlabeled data, pseudo-labeled data of a neural network model corresponding to another molecular representation in the plurality of molecular representations.

Abstract: Provided is an object determining method performed by a computer device, relating to the technical field of artificial intelligence. The method includes: acquiring index prediction values of objects in a first object set on a preset index respectively; determining, based on index experimental values and object features of the objects in the first object set on the preset index, a mapping relationship between the preset index and the object features; selecting, from the first object set, objects with the index prediction values satisfying index value screening conditions to obtain a second object set; and determining a target object meeting index requirements of the preset index from the second object set based on the mapping relationship.

Abstract: A chip preparation method and system, and a chip are provided. The method includes: preparing, by using a laser direct writing exposure manner, a first underlying circuit of an impedance Josephson parametric amplifier and a second underlying circuit for testing, to obtain a first chip product; generating, on the first chip product by using the laser direct writing exposure manner, a photoresist structure for preparing a Josephson junction; cutting, from the first chip product, a second chip product on which the second underlying circuit is located and a third chip product on which the first underlying circuit is located; preparing a Josephson junction sample based on a photoresist structure corresponding to the second underlying circuit, to obtain an oxidation condition; and preparing, according to the oxidation condition, the Josephson junction based on a photoresist structure corresponding to the first underlying circuit.

Abstract: A data classification method and system, and a classifier training method and system are disclosed in the embodiments of the present disclosure, belonging to the field of artificial intelligence (AI), cloud technologies, and quantum technologies. The method includes: providing to-be-classified data to a quantum computer; performing feature mapping on the to-be-classified data by using a quantum circuit to obtain a quantum state of the to-be-classified data; determining an estimation result according to a boundary vector of a classifier, the quantum state of the to-be-classified data, and a quantum state of index information corresponding to the boundary vector; transmitting the estimation result to a classical computer. The quantum state of the index information refers to a superposition of feature maps of training data used by the classifier during training; and determining a classification result corresponding to the to-be-classified data according to the estimation result.