Patents by Inventor Sheng YU

Sheng YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040001429
    Abstract: A wireless terminal and network terminal are provided for implementing a new uplink OFDM protocol. In the new protocol, the wireless terminal has a first transmit chain for generating and transmitting a low rate mode OFDM transmission in a first frequency band of the OFDM band; and a second transmit chain for generating and transmitting a burst-mode transmission in a second frequency band of the OFDM band, the first frequency band being distinct from the second frequency band. An access channel is provided which is overlaid over the low rate mode transmissions of other users.
    Type: Application
    Filed: April 4, 2003
    Publication date: January 1, 2004
    Inventors: Jianglei Ma, Wen Tong, Ming Jia, Peiying Zhu, Dong-Sheng Yu
  • Publication number: 20040002624
    Abstract: A ventricular apex connector for quick connection and disconnection of an inflow tube of a ventricular assist device, comprising a sewing ring, a cylindrical ring, gripping pins, a spring ring and a sealing O-ring is provided. The cylindrical ring defines two openings, diametrically opposed to each other, in its walls. Gripping pins, comprising rods with gripping pads, are placed in the openings in the cylindrical ring so that the gripping pads are at rest within the inner circumference of the cylindrical ring. The spring ring is placed around the cylindrical ring and the rods of the gripping pads, which extend out of the outer wall of the cylindrical ring, are welded to the spring ring. The gripping pins are thus biased towards each other by the force of the spring ring. When the spring ring is squeezed, at points away from the gripping pin connection points, the deformation of the spring ring causes the gripping pads to be pulled out towards the inner wall of the cylindrical ring.
    Type: Application
    Filed: June 26, 2002
    Publication date: January 1, 2004
    Inventors: Long Sheng Yu, Peter Piferi, Steven M. Parnis
  • Patent number: 6670275
    Abstract: A method for pulling back SiN to increase rounding effect in a shallow trench isolation process, includes the steps of preparing a substrate of Si and forming a SiO2 layer on the substrate, forming a Si3N4 layer on the SiO2 layer, defining Si3N4 trenches by plasma etching, etching the remaining Si3N4 with SF6/HBr gas, etching SiO2 layer to form a platform and enhance the rounding of the platform, etching the substrate to have a third shallow trench and a reinforced platform, filling the third shallow trench with oxide, planarizing the filled oxide using chemical mechanical polishing, and removing the Si3N4 layer, wherein after the removal of the Si3N4 layer, multiple cleaning processes are performed.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: December 30, 2003
    Assignee: Macronix International Co., Ltd
    Inventors: Chun-Hung Lee, Shiuh-Sheng Yu, Chia-Chi Chung
  • Patent number: 6664011
    Abstract: A new method is provided for the creation of contact holes. The DOF and MEF of closely packed holes can be improved using Alternating Phase Shifting Mask (Alt PSM) for the exposure of the holes. However, Alt PSM are dependent on hole density or hole separation and are less effective where holes are relatively further separated from each other. In order to improve DOF and MEF performance for the creation of holes, the invention adds extra holes to a given pattern of contact holes on the surface of a first mask, thus densifying the pattern of holes on the first mask and therefore reducing the range of the hole-diameter to hole separation ratio. The pattern of added holes is alternating in phase with the pattern of desired holes. The added holes will be filled up using a second mask.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: December 16, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Burn-Jeng Lin, Shinn-Sheng Yu, Bang-Chein Ho
  • Publication number: 20030224609
    Abstract: A method for pull back SiN to increase rounding effect in a shallow trench isolation process, includes the acts of preparing a substrate of Si and forming a SiO2 layer on the substrate, forming a Si3N4 layer on the SiO2 layer, defining Si3N4 trenches by plasma etching; etching the remaining Si3N4 with SF6/HBr gas, etching SiO2 layer to form a platform and enhance the rounding of the platform, etching the substrate to have a third shallow trench and a reinforced platform, filling the third shallow trench with oxide, leveling the oxide, which uses a CMP to level the filled oxide, and removing the Si3N4 layer, wherein after the removal of the Si3N4 layer, multiple cleaning processes are required.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Chun-Hung Lee, Shiuh-Sheng Yu, Chia-Chi Chung
  • Patent number: 6635579
    Abstract: An operating method of a semiconductor etcher includes three steps. The first step is to provide a first power for shortening a warm-up time of the etcher. The second step is to provide a second power, which is lower than the first power, to perform an etching process. The third step is to provide a third power, which is between the first and second power, for cleaning the etcher.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: October 21, 2003
    Assignee: Macronix International Co. Ltd.
    Inventors: Ming-Chung Liang, Shin-Yi Tsai, Hsu-Sheng Yu, Chun-Hung Lee
  • Publication number: 20030184228
    Abstract: A barrier rib structure for a plasma display panel is described. The barrier rib structure formed on a back substrate has a plurality of parallel barrier ribs. Each barrier rib has a plurality of nodes composed of two side-expanded trapezoid bulges. The barrier ribs are arranged according to the nodes to form a plurality of discharge spaces between the barrier ribs and a plurality of gas channels between the nodes to connect the discharge space.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 2, 2003
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Hsu-Pin Kao, Yi-Sheng Yu, Ching-Hui Lin, Kuang-Lang Chen, Sheng-Chi Lee
  • Publication number: 20030186555
    Abstract: The present invention is to utilize chemical dry etching technique to form a rounded corner in a shallow trench isolation process. After finishing the etching of the shallow trench, the present invention utilizes an isotropic etching step, which is a chemical dry etching step of a high silicon nitride to silicon etching selectivity, to pullback the silicon nitride layer to expose a silicon top corner. Then, the present invention utilizes an isotropic etching step, which is a chemical dry etching step of a high silicon to silicon nitride etching selectivity, to make the corner rounded to obtain a rounded corner of the shallow trench isolation structure. The present invention can avoid the formation of wrap rounding of the corner and prevent the formation of the short circuit or extraordinary electric behavior between adjacent devices and supply for performing following processes.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Ming-Chung Liang, Shtuh-Sheng Yu, Chun-Hung Lee, Shin-Yi Tsai
  • Publication number: 20030178938
    Abstract: A barrier rib structure for a plasma display panel is described. The barrier rib structure formed on a back substrate has a plurality of parallel barrier ribs. Each barrier rib has a plurality of discharge spaces therein divided by separate walls. Each of the discharge spaces is connected to a small gas channel beside the barrier rib through a small connect opening.
    Type: Application
    Filed: March 21, 2002
    Publication date: September 25, 2003
    Applicant: CHUNGHWA PICTURE TUBES
    Inventors: Hsu- Pin Kao, Yi-Sheng Yu, Ching-Hui Lin, Kuang-Lang Chen, Sheng-Chi Lee
  • Publication number: 20030174104
    Abstract: A color adjustment device and method for the plasma display panel. The color adjustment device comprises a look up table and an error diffusion circuit. Wherein, the look up table is used to store a plurality of gray scale data, select one corresponding data from the plurality of gray scale data according to a received gray scale input value as an output. The error diffusion circuit receives the gray scale data output from the look up table, and achieves the objective of improving the color adjustment precision by using an error diffusion compensation method.
    Type: Application
    Filed: July 31, 2002
    Publication date: September 18, 2003
    Inventors: Hsu-Pin Kao, Yi-Chia Shan, Chun-Hsu Lin, Yi-Sheng Yu
  • Publication number: 20030165654
    Abstract: An assist feature for isolated, and semi-dense random contacts, as may be present on a photomask used in photolithographic processes for semiconductor device fabrication, is disclosed. The assist feature can be used in conjunction with off-axis illumination (OAI) for such non-dense contacts, for improving the depth of focus (DOF), resolution, or both of photolithography for such contacts, such that the non-dense contact preferably substantially mimics a dense contact during OAI. A photomask of the invention includes a number of assist features situated near and around the non-dense contact. A method for creating a photomask according to the invention, as well as a method for fabricating a semiconductor device using such a mask, are also disclosed.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 4, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shinn-Sheng Yu
  • Publication number: 20030162364
    Abstract: A method of forming shallow trench isolation (STI) in a substrate. A shield layer is formed on part of the substrate. Using the shield layer as a mask, part of the substrate is removed to form a trench in the substrate. A first insulation layer is formed in part of the trench, where the trench remains an opening. The first insulation layer is partially etched back to leave a remaining first insulation layer at the bottom of the trench and to expose the sidewall of the trench above the remaining first insulation layer. The trench is filled up with a second insulation layer extending onto the shield layer. A planarization is performed on the second insulation layer, where the shield layer serves as a stop layer for the planarization. Thus, a void-free trench isolation area is formed in a substrate.
    Type: Application
    Filed: August 6, 2002
    Publication date: August 28, 2003
    Inventors: Ping-Wei Lin, Yao Sheng Yu, Ya-Lin Wang
  • Publication number: 20030162519
    Abstract: To reduce costs in multiple-input multiple-output (MIMO) transmit or receive diversity wireless communications systems an arrangement is described whereby the number of transmit or receive chains can be reduced. Switched antenna selection is used at the transmitter or receiver. Particular advantages are found for nomadic and high speed mobility MIMO user terminals where improvements in capacity are found. In addition improved ability to deal with the effects of spatial fading is achieved. Embodiments using directional antennas in combination with switched selection are also described. These are particularly advantageous for compact user equipment intended for nomadic or mobile use.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Inventors: Martin Smith, Dean Kitchener, Sonya Amos, Dawn Power, Dong-Sheng Yu, Ming Jia, Jianglei Ma, Peiying Zhu, Wen Tong
  • Publication number: 20030157808
    Abstract: Photoresist reflow for an enhanced process window for non-dense contacts is disclosed. A corrective bias is determined for application to each of a number of contacts at different pitches, to achieve a substantially identical critical dimension for each contact. The corrective bias is determined based on a first and a second critical dimension for each contact, where the first critical dimension is before photoresist reflow, and potentially inclusive of optical proximity effects, and the second critical dimension is after photoresist reflow. A photomask is then constructed for a semiconductor design that incorporates the corrective bias that has been determined for the contacts of the design. Lithographical processing of the semiconductor design on a semiconductor wafer using thus photomask, and subsequent photoresist reflow, thus achieves a substantially identical critical dimension for each of the contacts of the semiconductor design.
    Type: Application
    Filed: February 16, 2002
    Publication date: August 21, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Tai Lin, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 6607456
    Abstract: A self-luminous basket net being hung to an iron basket ring of a basket board is disclosed. The self-luminous basket net comprises a fabric rope, which is fabricated to be formed with as a lower half basket net with a plurality of basket meshes and an upper half basket net formed by a plurality of basket meshes; the plurality of basket meshes of the upper half basket net is self-luminous which is fabricated by a self-luminous plastic monofilament and hung from the iron basket ring; the basket net emits light at night so that the shooter can view the position of the basket net.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: August 19, 2003
    Inventor: Wan-Sheng Yu
  • Publication number: 20030134205
    Abstract: Maximizing a common process window for optical proximity correction (OPC)-modified features of a semiconductor design having varying pitch is disclosed. For each pitch within a semiconductor design, a bias needed at the pitch that maximizes a common process window for the number of pitches given a critical dimension (CD) specification for a semiconductor design of the photomask is determined. The original layout for the semiconductor design of the photomask is then modified by performing rule-based optical-proximity correction (OPC), including adding the bias determined at each pitch, to yield a modified layout for the semiconductor design of the photomask. The modified layout is further modified by performing model-based on the modified layout such that exposed semiconductor wafer CD's at each pitch are at least substantially equal to the CD specification for the pitch, to yield a final layout for the semiconductor design of the photomask.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shinn-Sheng Yu
  • Publication number: 20030104286
    Abstract: A new method is provided for the creation of contact holes. The DOF and MEF of closely packed holes can be improved using Alternating Phase Shifting Mask (Alt PSM) for the exposure of the holes. However, Alt PSM are dependent on hole density or hole separation and are less effective where holes are relatively further separated from each other. In order to improve DOF and MEF performance for the creation of holes, the invention adds extra holes to a given pattern of contact holes on the surface of a first mask, thus densifying the pattern of holes on the first mask and therefore reducing the range of the hole-diameter to hole separation ratio. The pattern of added holes is alternating in phase with the pattern of desired holes. The added holes will be filled up using a second mask.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 5, 2003
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Burn-Jeng Lin, Shinn-Sheng Yu, Bang-Chein Ho
  • Publication number: 20030104319
    Abstract: A new method is provided for the creation of contact holes. The invention provides two masks. The first mask, referred to as the packed mask, comprises the desired contact holes, which are part of the creation of a semiconductor device. To the packed mask are added padding holes in order to increase the hole density of the packed mask. The second mask, referred to an the unpacking mask, comprises openings at the same locations as the locations of the padding holes of the first mask, the openings provided in the second mask have slightly larger dimensions than the padding holes of the first mask. A first exposure is made using the packed mask, a second exposure of the same surface area is made using the unpacking mask. The unpacking mask is used to selectively cover the padding contact holes, resulting in the final image.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Burn J. Lin, Shinn-Sheng Yu, Bang Chein Ho
  • Patent number: 6551899
    Abstract: A method for fabricating nonvolatile memory devices includes forming one or more polyislands, each having a conductive layer and a dielectric layer, on a dielectric layer of a substrate before the creation of control gates on the memory device. In particular, the polyislands may be formed by providing a substrate with a dielectric layer on a surface of the substrate, and forming one or more bar-like structures on the substrate. Each of the bar-like structures includes a conductive layer and a dielectric layer. The bar-like structures are then patterned with compositions having various etching sensitivities for the components of the bar-like structures, to thereby create one or more polyislands before the addition of a second conductive layer over the resulting structure.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: April 22, 2003
    Inventors: Hsu-Sheng Yu, Chun-Hung Lee
  • Patent number: D484932
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: January 6, 2004
    Inventor: Wan Sheng Yu