Abstract: A controller having a wireless transmission interface is provided. The controller includes an amplifier, an analog-to-digital converter, a digital filter, a processor, and a radio frequency signal transceiver. The amplifier is coupled to the wireless transmission interface, and generates an amplification signal according to an input signal. The analog-to-digital converter is coupled to the amplifier, and configured to convert the amplification signal into a digital format. The digital filter is coupled to the analog-to-digital converter, and configured to filter the amplification signal in the digital format to generate a filtered signal. The processor is coupled to the digital filter, and configured to perform a calculation on the filtered signal to generate a calculation result. The radio frequency signal transceiver is coupled to the processor, and obtains received information according to the calculation result and the filtered signal.

Abstract: A controller having a wireless transmission interface is provided. The controller includes an amplifier, an analog-to-digital converter, a digital filter, a processor, and a radio frequency signal transceiver. The amplifier is coupled to the wireless transmission interface, and generates an amplification signal according to an input signal. The analog-to-digital converter is coupled to the amplifier, and configured to convert the amplification signal into a digital format. The digital filter is coupled to the analog-to-digital converter, and configured to filter the amplification signal in the digital format to generate a filtered signal. The processor is coupled to the digital filter, and configured to perform a calculation on the filtered signal to generate a calculation result. The radio frequency signal transceiver is coupled to the processor, and obtains received information according to the calculation result and the filtered signal.

Abstract: A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and two address fields. The two operation fields indicate the type of operation in accessing the memory. One of the address fields includes a first upper address corresponding to the first memory block and a first lower address corresponding to a first memory unit of the first memory block. The other one of the two address fields includes a second upper address corresponding to the second memory block and a second lower address corresponding to a second memory unit of the second memory block. Then, whether two instructions are performing the same type of operation on the same memory block is determined. If yes, the type of operation indicated by the two operation fields is performed on the corresponding memory block parallelly.

Abstract: A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and two address fields. The two operation fields indicate the type of operation in accessing the memory. One of the address fields includes a first upper address corresponding to the first memory block and a first lower address corresponding to a first memory unit of the first memory block. The other one of the two address fields includes a second upper address corresponding to the second memory block and a second lower address corresponding to a second memory unit of the second memory block. Then, whether two instructions are performing the same type of operation on the same memory block is determined. If yes, the type of operation indicated by the two operation fields is performed on the corresponding memory block parallelly.

Abstract: A data storing method applied to a processor having a pipelined processing unit is provided. The pipelined processing unit includes stages. The stages include a source operand fetch stage and a write-back stage. The method includes the following steps. Firstly, a storing instruction is fetched and decoded. Next, the storing instruction is entered to the source operand fetch stage, and whether there is a late-done instruction in the pipelined processing unit is determined. The late-done instruction not lagged behind the storing instruction generates a late-coming result before entering the write-back stage. If it is determined that there is a late-done instruction in the pipelined processing unit, then the late-coming result is fetched before the storing instruction is entered to the write-back stage. Thereafter, the storing instruction is entered to the write-back stage, and the late-coming result is stored to a target memory which the storing instruction corresponds to.