Abstract: A control device adapted to control a first light-emitting diode and a second light-emitting diode, includes a first logic operation unit receiving a first enable signal and a second enable signal to generate a first logic signal, a second logic operation unit receiving the first and second enable signals to generate a second logic signal, a first adjustment unit generating a first adjustment signal according to the first logic signal, a second adjustment unit generating a second adjustment signal according to the second logic signal, a first control unit outputting a first control signal to the first light-emitting diode according to the first enable signal and the first adjustment signal, and a second control unit outputting a second control signal to the second light-emitting diode according to the second enable signal and the second adjustment signal. The first logic signal and the second logic signal are complementary.

Abstract: A control device adapted to control a first light-emitting diode and a second light-emitting diode, includes a first logic operation unit receiving a first enable signal and a second enable signal to generate a first logic signal, a second logic operation unit receiving the first and second enable signals to generate a second logic signal, a first adjustment unit generating a first adjustment signal according to the first logic signal, a second adjustment unit generating a second adjustment signal according to the second logic signal, a first control unit outputting a first control signal to the first light-emitting diode according to the first enable signal and the first adjustment signal, and a second control unit outputting a second control signal to the second light-emitting diode according to the second enable signal and the second adjustment signal. The first logic signal and the second logic signal are complementary.

Abstract: A method for reset a register includes the following step: a computer starts to be booted and perform a booting procedure. Wherein, the computer includes at least one register. Power is supplied to the at least one register. Determine if the computer is booted successfully. If it is determined that the computer fails to be booted, the at least one register is kept to be grounded for a predetermined period of time to reset the at least one register. After the at least one register is grounded, power is supplied to the at least one register again, and the computer is rebooted.

Abstract: A method for reset a register includes the following step: a computer starts to be booted and perform a booting procedure. Wherein, the computer includes at least one register. Power is supplied to the at least one register. Determine if the computer is booted successfully. If it is determined that the computer fails to be booted, the at least one register is kept to be grounded for a predetermined period of time to reset the at least one register. After the at least one register is grounded, power is supplied to the at least one register again, and the computer is rebooted.

Abstract: A test board is provided. The test board includes a power connecting interface, diode modules, a power module a detecting module, and a processor. The power connecting interface includes power pins, wherein each of the power pins is electrically connected to a motherboard power socket to receive a power signal. Each of the diode modules is electrically connected to one of the power pins and includes at least one diode. The power module is electrically connected to the diode modules to receive the power signal through each of the diode modules. The detection module is electrically connected to points between the diode modules and the power connecting interface to generate a detection result according to the voltage between each diode module and the power connecting interface. The processor is used to determine the connecting state between the power pin and the corresponding motherboard power socket according to the detection result.

Abstract: A test board is provided. The test board includes a power connecting interface, diode modules, a power module a detecting module, and a processor. The power connecting interface includes power pins, wherein each of the power pins is electrically connected to a motherboard power socket to receive a power signal. Each of the diode modules is electrically connected to one of the power pins and includes at least one diode. The power module is electrically connected to the diode modules to receive the power signal through each of the diode modules. The detection module is electrically connected to points between the diode modules and the power connecting interface to generate a detection result according to the voltage between each diode module and the power connecting interface. The processor is used to determine the connecting state between the power pin and the corresponding motherboard power socket according to the detection result.

Abstract: A multiprocessor power-on switch circuit applied to a mainboard having multiple power-on circuits is provided, in which each power-on circuit includes a peripheral circuit corresponding to a processor. A selection circuit in the power-on switch circuit is responsible for selecting a power-on circuit as a first power-on circuit or a second power-on circuit. When the mainboard is powered on, a detection circuit in the power-on switch circuit receives a status signal from the first power-on circuit performing the power-on action. When the status signal is determined as a fault signal by the detection circuit, a control signal is output to the selection circuit, so as to make the selection circuit set the second power-on circuit as the power-on circuit to actuate the mainboard.

Abstract: A recording method for writing data into an electrically erasable programmable read-only memory is disclosed, in which the memory has already been electrically connected to a controller through a logic device. The method sets the logic devices for the first time to disconnect the memory from the controller, and set the logic devices for the second time to write setting data required by the controller into the memory. After that, the method reads out the setting data stored in the memory to confirm the writing of the setting data, and connects the memory to the controller again.

Abstract: A pin setting circuit and a clock driving circuit are disclosed. The clock pin setting circuit sets the clock pin of the clock driving circuit. The pin setting circuit includes the double one-shot circuit and the switch circuit. The double one-shot circuit includes the first one-shot circuit and the second one-shot circuit. The first one-shot circuit receives a clock signal and generates a first control signal according to the frequency of the clock signal. The second circuit outputs a second control signal according to the first control signal generated. The switch circuit sets the clock pin to the power end or the ground end according to the second control signal.

Abstract: The present invention discloses a machine for programming on-board chipsets, wherein the on-board chipsets means that some chipsets are mounted on a circuit board, and the circuit board has a plurality of input pads electrically connected to each chipset individually. The machine comprises a platform, a number of programming modules and an IC programming burner in which the platform faces a surface of the circuit board having the input pads, the programming modules disposed movably on the platform separately extends a number of output pins outwardly so that for connecting electrically an input pad as contacting the input pad, and the IC programming burner electrically connected to each of the programming modules separately distributes a set of programming codes into each programming module when the output pins electrically connect to the input pads.

Abstract: The bonding pad structure includes a main bonding pad and a blank path. The blank path crosses through the main bonding pad for dividing the main bonding pad into a first sub-bonding pad and a second sub-bonding pad. The bonding pad structure may further include a solder covered on the blank path and the main bonding pad selectively. The main bonding pad is regarded as a closed circuit when the solder is covered on the blank path and the main bonding pad. The main bonding pad is regarded as a open circuit when the solder is not covered on the blank path and the main bonding pad. A debug method with the bonding pad structure is also disclosed.

Abstract: An abnormal power interruption internal circuitry protection method and system is proposed for use with a computer platform, such as a blade server, which is characterized by the utilization of each server module's identification code (i.e., blade ID signal) and power-good signal to judge whether each server module is subjected to an abnormal power interruption, such that in the event of the abnormal power interruption, a small amount of remnant electrical power left in the internal circuitry of the blade server can be fetched as power source to shut down the server modules through a normal shutdown procedure. This feature can help protect the internal circuitry of the server modules of the blade server from being damaged due to abnormal shutdown in the event of abnormal power interruption.

Abstract: A multi-level voltage detection circuit includes the comparators, the first resistors, the power signal input port and the or-gate. The first resistors and the power signal input port are electrically connected to the comparators. The or-gate is electrically connected to the outputs of the comparators. The or-gate outputs the power good signal according to the comparing result of the comparators.

Abstract: An expanding high speed transport interface hardware method for motherboard is provided. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket. Besides, more design choices and opportunities are provided for the manufacturers of motherboard and peripheral.

Abstract: A multiprocessor power-on switch circuit applied to a mainboard having multiple power-on circuits is provided, in which each power-on circuit includes a peripheral circuit corresponding to a processor. A selection circuit in the power-on switch circuit is responsible for selecting a power-on circuit as a first power-on circuit or a second power-on circuit. When the mainboard is powered on, a detection circuit in the power-on switch circuit receives a status signal from the first power-on circuit performing the power-on action. When the status signal is determined as a fault signal by the detection circuit, a control signal is output to the selection circuit, so as to make the selection circuit set the second power-on circuit as the power-on circuit to actuate the mainboard.

Abstract: A detection device and a method therefor are provided. The detection device is used to activate the main-board, when the power-on interval of the main-board is equal to the predetermined power-on interval. The detection device compares the value of the status signal transmitted with the predetermined status value. In case that the two values are not equal, the detection device generates and displays a first error message; otherwise, in case that the two values are equal, then the detection device powers-off the main-board, and upon determining that the voltage after its power-off is not equal to zero voltage, the detection device generates and displays a second error message; and upon determining that the accumulated detection number is not equal to the predetermined detection number, the detection device will reactivate the main-board and repeats the above steps, after the power-off interval of the main-board has reached to the predetermined power-off interval.

Abstract: An expansion structure of memory module slots is provided. A circuit switch board and a substrate are disposed on a motherboard, wherein a plurality of first memory module slots is disposed on the motherboard, at least one second memory module slot is disposed on one side of the substrate, and a plurality of third memory module slots is disposed on the other side of the substrate. The third memory module slots are electrically connected to the second memory module slot, and two ends of the circuit switch board are plugged into one of the first memory module slots and the second memory module slot. When memory modules are plugged in the third memory module slots, the memory modules are electrically connected to the first memory module slots respectively through the circuit switch board and then transmit data and signals with the motherboard.

Abstract: An abnormal power interruption internal circuitry protection method and system is proposed for use with a computer platform, such as a blade server, which is characterized by the utilization of each server module's identification code (i.e., blade ID signal) and power-good signal to judge whether each server module is subjected to an abnormal power interruption, such that in the event of the abnormal power interruption, a small amount of remnant electrical power left in the internal circuitry of the blade server can be fetched as power source to shut down the server modules through a normal shutdown procedure. This feature can help protect the internal circuitry of the server modules of the blade server from being damaged due to abnormal shutdown in the event of abnormal power interruption.

Abstract: An expanding high speed transport interface hardware method for motherboard is provided. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket. Besides, more design choices and opportunities are provided for the manufacturers of motherboard and peripheral.

Abstract: Disclosed is a PCI mezzanine card (PMC) with pin-grid-array (PGA) which can be applied onto a two or more central processing unit (CPU) socket equipped mother board When one of the CPU sockets is not installed with a CPU, the PMC communicates with the mother board through the CPU socket with its PGA interface. An IC package mounted on the PMC can communicate with the mother board through the PMC.