Abstract: The present disclosure provides a method for optimizing parameters of a ladder-type carbon trading mechanism based on an improved particle swarm optimization (IPSO) algorithm. The method first obtains information and operating data of a park-level integrated energy system, establishes equipment models and constraints of the park-level integrated energy system, and establishes a ladder-type carbon trading model; then encapsulates a process of optimized low-carbon dispatching of the park-level integrated energy system as a fitness function whose input is parameters of a carbon trading mechanism and output is a carbon emission of the system; and finally, introduces an IPSO algorithm to optimize the fitness function, and outputs optimization result information of the algorithm. The present disclosure verifies effectiveness and rationality of the model and the method that give full play to a role of the ladder-type carbon trading mechanism in the park-level integrated energy system through example analysis.

Abstract: A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

Abstract: The present disclosure generally relates to determining a process condition in a semiconductor process using attribute-relative process conditions. An example is a method of forming an integrated circuit (IC). First and second historical process conditions are obtained. The first historical process conditions are of previous semiconductor processing corresponding to a target value of a process attribute for forming the IC, and the second historical process conditions are of previous semiconductor processing corresponding to variable values of the process attribute. Attribute-relative process conditions are calculated. Each attribute-relative process condition is based on the first historical process conditions and the second historical process conditions that correspond to a respective given value of the variable values. An average process condition is determined from a subset of the attribute-relative process conditions.

Abstract: A semiconductor device assembly including a substrate, a surface-mount device (SMD) electrical component attached to the substrate is provided. The SMD electrical component includes a first contact and a second contact, and at least a first wire bond electrically and physically coupled directly to the first contact.

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor devices include a package substrate, a stack of dies carried by the package substrate, and one or more radiation shields configured to absorb neutrons from neutron radiation incident on the semiconductor device. The radiation shields can include one or more walls attached to a perimeter portion of the package substrate at least partially surrounding the stack of dies and/or a lid carried over the stack of dies. Each of the radiation shields can include hydrocarbon materials, boron, lithium, gadolinium, cadmium, and like materials that effectively absorb neutrons from neutron radiation. In some embodiments, the semiconductor devices also include a molding material over the stack of dies and the radiation shields, and a hydrocarbon coating over an external surface of the mold material.

Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.

Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Abstract: A conical structure of cubic Boron Nitride (cBN) is formed on a diamond layered substrate. A method of forming the cBN structure includes steps of (a) forming diamond nuclei on a substrate, (b) growing a layer of diamond film on the substrate, (c) depositing a cBN film on said diamond layer, (d) pre-depositing nanoscale etching masks on the cBN film, and (e) etching the deposited cBN film. In particular, though not exclusively, the cubic Boron Nitride structure has great potential applications in probe analytical and testing techniques including scanning probe microscopy (SPM) and nanoindentation, nanomechanics and nanomachining in progressing microelectromechanical system (MEMS) and nanoelectyromechanical system (NEMS) devices, field electron emission, vacuum microelectronic devices, sensors and different electrode systems including those used in electrochemistry.

Abstract: A method for fabricating diamond nanopillars includes forming a diamond film on a substrate, depositing a metal mask layer on the diamond film, and etching the diamond film coated with the metal mask layer to form diamond nanopillars below the mask layer. The method may also comprise forming diamond nuclei on the substrate prior to forming the diamond film. Typically, a semiconductor substrate, an insulating substrate, a metal substrate, or an alloy substrate is used.

Abstract: A conical structure of cubic Boron Nitride (cBN) is formed on a diamond layered substrate. A method of forming the cBN structure includes steps of (a) forming diamond nuclei on a substrate, (b) growing a layer of diamond film on the substrate, (c) depositing a cBN film on said diamond layer, (d) pre-depositing nanoscale etching masks on the the cBN film, and (e) etching the the deposited cBN film. In particular, though not exclusively, the cubic Boron Nitride structure has great potential applications in probe analytical and testing techniques including scanning probe microscopy (SPM) and nanoindentation, nanomechanics and nanomachining in progressing microelectromechanical system (MEMS) and nanoelectyromechanical system (NEMS) devices, field electron emission, vacuum microelectronic devices, sensors and different electrode systems including those used in electrochemistry.

Abstract: A method for fabricating diamond nanopillars includes forming a diamond film on a substrate, depositing a metal mask layer on the diamond film, and etching the diamond film coated with the metal mask layer to form diamond nanopillars below the mask layer. The method may also comprise forming diamond nuclei on the substrate prior to forming the diamond film. Typically, a semiconductor substrate, an insulating substrate, a metal substrate, or an alloy substrate is used.

Abstract: A surface acoustic wave (SAW) device which is made of cBN/diamond composite structures and the fabrication method are disclosed. In the SAW device based on cubic boron nitride and diamond composite structures, the diamond hard layer includes randomly-oriented polycrystalline diamond (poly-D), oriented (heteroepitaxial) diamond, single-crystal diamond wafers and nanocrystalline diamond (nano-D) films. The cBN film with a sound velocity close to that of diamond serves as the piezoelectric layer, which was directly deposited on diamond hard layer without any soft sp2-BN incubation layer by ion assisted physical vapor deposition (PVD) and plasma-enhanced (or ion assisted) chemical vapor deposition (PECVD). Due to the high sound velocity and the low velocity dispersion between the cBN and diamond layered materials, the present SAW device based on cubic boron nitride and diamond composite structures can improve the device performance and operate at ultra-high frequency range.

Abstract: A surface acoustic wave (SAW) device which is made of cBN/diamond composite structures and the fabrication method are disclosed. In the SAW device based on cubic boron nitride and diamond composite structures, the diamond hard layer includes randomly-oriented polycrystalline diamond (poly-D), oriented (heteroepitaxial) diamond, single-crystal diamond wafers and nanocrystalline diamond (nano-D) films. The cBN film with a sound velocity close to that of diamond serves as the piezoelectric layer, which was directly deposited on diamond hard layer without any soft sp2-BN incubation layer by ion assisted physical vapor deposition (PVD) and plasma-enhanced (or ion assisted) chemical vapor deposition (PECVD). Due to the high sound velocity and the low velocity dispersion between the cBN and diamond layered materials, the present SAW device based on cubic boron nitride and diamond composite structures can improve the device performance and operate at ultra-high frequency range.