Patents by Inventor Sheng-Bin Lin

Sheng-Bin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock jitter measurement circuit and integrated circuit having the same
    Patent number: 7945404
    Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: May 17, 2011
    Assignee: Faraday Technology Corp.
    Inventors: Jung-Chi Ho, Sheng-Bin Lin, Yeong-Jar Chang
  • CLOCK JITTER MEASUREMENT CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME
    Publication number: 20090271133
    Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Jung-Chi Ho, Sheng-Bin Lin, Yeong-Jar Chang