Abstract: Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.

Abstract: Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.

Abstract: A memory cell includes a substrate including a first diode region, a second diode region, a third diode region, and a fourth diode region, a first well region formed in the first diode region and the second diode region, a second well region formed in the third diode region and the fourth diode region, a doped conductive region formed on the first well region and the second well region, and a deep trench isolation structure formed in the substrate to electrically isolate different portions of each of the first well region, the second well region, and the doped conductive region formed over different diode regions. The second well region and the first well region have different doping types. The memory cell includes a resistance random access memory device formed over the substrate and electrically connected to the doped conductive region in the second diode region and the third diode region.

Abstract: A memory cell includes a bit line and a reset line sharing a same line, a word line, a first diode including a first N-well region in a substrate, and a first P-type doped region adjacent to the first N-well region that is coupled to a set line, a second diode spaced apart from the first diode and including a second N-well region in the substrate, a first N-type doped region and a second P-type doped region spaced apart from each other and adjacent to the second N-well region, the second P-type doped region coupled to the bit line and the reset line, a bottom electrode coupled to the first P-type doped region and the first N-type doped region, a top electrode coupled to the word line, and a data storage material layer disposed between the bottom electrode and the top electrode.

Abstract: A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. The flash memory device may be formed on a dielectric layer, and its fabrication process is thus compatible with back end of line processes.

Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

Abstract: Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode.

Abstract: Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.

Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

Abstract: A memory cell includes a bit line and a reset line sharing a same line, a word line, a first diode including a first N-well region in a substrate, and a first P-type doped region adjacent to the first N-well region that is coupled to a set line, a second diode spaced apart from the first diode and including a second N-well region in the substrate, a first N-type doped region and a second P-type doped region spaced apart from each other and adjacent to the second N-well region, the second P-type doped region coupled to the bit line and the reset line, a bottom electrode coupled to the first P-type doped region and the first N-type doped region, a top electrode coupled to the word line, and a data storage material layer disposed between the bottom electrode and the top electrode.

Abstract: Various embodiments provide memory devices and methods for forming the same. In an exemplary method, a provided substrate has one or more memory cells, a memory cell of which includes a control gate layer. The control gate layer has a first portion and a second portion on the first portion. A silicide layer is formed in the control gate layer and covers at least a sidewall of the second portion. A portion of the silicide layer is removed to reduce a size of the silicide layer in a direction parallel to the substrate. A fourth dielectric layer is formed on the substrate and on the memory cell, and has a top surface higher than a top surface of the memory cell. An opening is formed in the fourth dielectric layer and exposes a portion of the substrate between adjacent memory cells. A conductive structure is formed in the opening.

Abstract: A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.

Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

Abstract: Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode.

Abstract: A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. The method also includes forming a plurality of stacked structures by etching the stacked layer and the substrate, where the spacing between the adjacent stacked structures forms a plurality of parallel first trenches. In addition, the method includes forming a plurality of second trenches and forming a plurality of third trenches. Moreover, the method includes forming a second dielectric layer on the floating gate layer and the side wall and bottom of the third trenches and forming a control gate layer on the second dielectric layer. Further, the method includes forming a plurality of fourth trenches and removing the sacrificial layer along the fourth trenches.

Abstract: A memory cell includes a substrate including a first diode region, a second diode region, a third diode region, and a fourth diode region, a first well region formed in the first diode region and the second diode region, a second well region formed in the third diode region and the fourth diode region, a doped conductive region formed on the first well region and the second well region, and a deep trench isolation structure formed in the substrate to electrically isolate different portions of each of the first well region, the second well region, and the doped conductive region formed over different diode regions. The second well region and the first well region have different doping types. The memory cell includes a resistance random access memory device formed over the substrate and electrically connected to the doped conductive region in the second diode region and the third diode region.

Abstract: A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.

Abstract: Flash memory devices and fabrication methods thereof are provided. An exemplary method includes providing discrete bit lines on a semiconductor substrate, a first dielectric layer on top surfaces of the bit lines, and a floating gate structure on the first dielectric layer, trenches being formed between adjacent bit lines and on the semiconductor substrate; forming a sacrificial layer with a top surface above the top surfaces of the bit lines in the trenches; forming a second dielectric layer on top and side surfaces of the floating gate structure and the top surface of the sacrificial layer; forming a control gate structure on the second dielectric layer; removing portions of the second dielectric layer, the floating gate structure and the first dielectric layer to expose a portion of the sacrificial layer; and removing the sacrificial layer from the adjacent bit lines and the semiconductor substrate, thereby forming air gaps.

Abstract: A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. The method also includes forming a plurality of stacked structures by etching the stacked layer and the substrate, where the spacing between the adjacent stacked structures forms a plurality of parallel first trenches. In addition, the method includes forming a plurality of second trenches and forming a plurality of third trenches. Moreover, the method includes forming a second dielectric layer on the floating gate layer and the side wall and bottom of the third trenches and forming a control gate layer on the second dielectric layer. Further, the method includes forming a plurality of fourth trenches and removing the sacrificial layer along the fourth trenches.

Abstract: A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. The flash memory device may be formed on a dielectric layer, and its fabrication process is thus compatible with back end of line processes.