Abstract: Embodiments of the present invention are directed to providing a time delay to a shortened trace in a differential microstrip trace pair. By adding back metal to a ground plane associated with a DC blocking capacitor, a time delay can be added to the shortened trace. The cutout associated with the longer trace remains unaltered. In a further embodiment, both cutouts can be modified with the addition of metal, with the cutout associated with the shorter trace receiving more metal than the other cutout. In a further embodiment of the present invention, a cutout associated with a connector can be modified to add back metal in the cutout. The cutout associated with the shorter trace is modified while the other cutout is left unchanged.

Abstract: Embodiments of the present invention are directed to providing an increased trace width when traversing a void in another layer in a printed circuit board or package design. By increasing the trace width or alternatively increasing the capacitance, the degradation due to the void can be reduced. This approach works for microstrip, stripline as well as other transmission lines that use a reference plane. The void can be the result of an antipad associated with a via, or any other disruption in an otherwise uniform reference plane.

Abstract: A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.

Abstract: A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.

Abstract: Embodiments of the present invention are directed to providing an increased trace width when traversing a void in another layer in a printed circuit board or package design. By increasing the trace width or alternatively increasing the capacitance, the degradation due to the void can be reduced. This approach works for microstrip, stripline as well as other transmission lines that use a reference plane. The void can be the result of an antipad associated with a via, or any other disruption in an otherwise uniform reference plane.

Abstract: Embodiments of the present invention are directed to providing a time delay to a shortened trace in a differential microstrip trace pair. By adding back metal to a ground plane associated with a DC blocking capacitor, a time delay can be added to the shortened trace. The cutout associated with the longer trace remains unaltered. In a further embodiment, both cutouts can be modified with the addition of metal, with the cutout associated with the shorter trace receiving more metal than the other cutout. In a further embodiment of the present invention, a cutout associated with a connector can be modified to add back metal in the cutout. The cutout associated with the shorter trace is modified while the other cutout is left unchanged.

Abstract: A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.

Abstract: A multi-band antenna comprises a first conductive layer having one or more parasitic patches, a second conductive layer having a plurality of radiating patches, and a third conductive layer having a ground patch. The first, second and third conductive layers may be separated by first and second substrate layers. The second conductive layer may comprise a first radiating patch having dimensions selected to radiate signals within a first frequency spectrum and second radiating patches having dimensions selected to radiate signals within a second frequency spectrum. In wireless local area network (WLAN) embodiments, the first frequency spectrum may comprise a frequency band ranging from approximately 5.1 to 5.9 GHz, and the second frequency spectrum may comprise frequency bands ranging from approximately 2.4 to 2.5 GHz.

Abstract: A multi-band antenna comprises a first conductive layer having one or more parasitic patches, a second conductive layer having a plurality of radiating patches, and a third conductive layer having a ground patch. The first, second and third conductive layers may be separated by first and second substrate layers. The second conductive layer may comprise a first radiating patch having dimensions selected to radiate signals within a first frequency spectrum and second radiating patches having dimensions selected to radiate signals within a second frequency spectrum. In wireless local area network (WLAN) embodiments, the first frequency spectrum may comprise a frequency band ranging from approximately 5.1 to 5.9 GHz, and the second frequency spectrum may comprise frequency bands ranging from approximately 2.4 to 2.5 GHz.