Abstract: Techniques to monitor multiple targets with a single camera are disclosed. In one embodiment, an image sensor is provided with two or more readout circuits, each operating independently and is designed to read out charges from a designated area of the image sensor. When two or more designated sensing areas in the image sensor are being focused onto different objects and read out respectively, such an image sensor is capable of monitoring multiple targets. When placed in traffic surveillance, a camera equipped with such an image sensor is able to monitor multiple forward and backward lanes in near or far field. Further with the control of the designated areas, different resolutions of the images may be produced.

Abstract: Designs of multi-band sensor array to generate multi-spectral images are disclosed. According to one aspect of the present invention, a multi-band sensor array includes one linear sensor configured to sense a scene in panchromatic spectrum to produce a panchromatic (PAN) sensing signal, and four color-band linear sensors to sense the same scene in different color bands to produce respective sensing signals. These sensors are packaged in a single module that is disposed on a single optical plane when used to scan a scene. A multi-spectral image is produced by combining these sensing signals. Further a unique packaging of the sensor array and a combination of soft and hard PCB are disclosed to withstand extremes in a harsh environment.

Abstract: Designs of multi-band sensor array to generate multi-spectral images are disclosed. According to one aspect of the present invention, a multi-band sensor array includes one linear sensor configured to sense a scene in panchromatic spectrum to produce a panchromatic (PAN) sensing signal, and four color-band linear sensors to sense the same scene in different color bands to produce respective sensing signals. These sensors are packaged in a single module that is disposed on a single optical plane when used to scan a scene. A multi-spectral image is produced by combining these sensing signals. Further a unique packaging of the sensor array and a combination of soft and hard PCB are disclosed to withstand extremes in a harsh environment.

Abstract: Designs of image sensors with subpixels are disclosed. According to one aspect of an image sensor in one embodiment, subpixels within a pixel are designed without significantly increasing the cell or pixel area of the pixel. The readouts from the subpixels are accumulated to increase the sensitivity of the pixel without increasing the area of the image sensor. According to another aspect of the image sensors in the present invention, some subpixels within a pixel are respectively coated with filters, each designed for a frequency range. Thus the frequency response of a CMOS image sensor can be enhanced significantly according to application.

Abstract: Techniques to monitor multiple targets with a single camera are disclosed. In one embodiment, an image sensor is provided with two or more readout circuits, each operating independently and is designed to read out charges from a designated area of the image sensor. When two or more designated sensing areas in the image sensor are being focused onto different objects and read out respectively, such an image sensor is capable of monitoring multiple targets. When placed in traffic surveillance, a camera equipped with such an image sensor is able to monitor multiple forward and backward lanes in near or far field. Further with the control of the designated areas, different resolutions of the images may be produced.

Abstract: A multi-pixel row wafer-scale cluster image sensor chip (WCISC) is proposed. Expressed in X-Y-Z coordinates with its pixel rows along X-axis, the WCISC converts areal image frame (IMFM) into areal image frame signal (AIFS). The WCISC includes multiple imaging pixel rows PXRW1, . . . , PXRWM. Each PXRWi has photoelectrical sensing elements spanning pixel row width PRWi and producing a pixel row image signal PRISi. Each PXRWi is offset from PXRW1 by distance XOFSTi and spaced from PXRWi?1 by distance SPi?1,I such that X- and Y-extremities of (PXRW1, . . . , PXRWM) define IMFM. The WCISC is so configured that any image pixel sweeping through IMFM will be sensed by at least one imaging pixel row. In the presence of Y-directional relative motion between WCISC and IMFM and an external electronic imaging controller (EEIC) interfacing with the WCISC, the EEIC can extract all PRISi from WCISC and reconstruct the AIFS.

Abstract: A wafer-scale linear image sensor chip (WLISC) is proposed with gapless pixel line and signal readout circuit segments. The WLISC converts pixel line image (PLI) of length LPL into line image signal (LIS). The WLISC includes a linear array of sensor segments. Each sensor segment includes a gapless local pixel line segment (LPLSj) of sensing elements. The LPLSj converts portion of the PLI into a raw image segment signal set (RISSj). The LPLSj set forms a gapless global pixel line (GPL) corresponding to PLI. The sensor segment also includes readout circuit segment (RCSj) coupled to LPLSj for processing RISSj into a readout image segment signal set (ROSSj). The RCSj has a set of contact pads (CTPj) for off-chip interconnection. Upon off-chip interconnection of the CTPj set thus composing the ROSSj set into LIS, the WLISC functions as a key part of a linear image sensor system of image length LPL.

Abstract: A long-length industry camera image sensor (LICIS) is proposed for, expressed in X-Y-Z coordinates, converting a pixel line image (PLI) of length LPL along X-direction into a line image signal (LIS). The LICIS includes a full-width linear image sensor (FLIS) of length LIS along X-direction and displaced from the PLI along Z-direction by an imaging distance DIMG for converting an incident line image (ILI) impinging upon its FLIS top surface into the LIS. Where LIS is about equal to LPL. The LICIS also has a full-width linear rod lens (FLRL) of length LRL along X-direction and displaced from the PLI in Z-direction by a working distance DWKG. Where LRL is about equal to LPL and DWKG is selected such that the PLI gets focused by the FLRL into the ILI at the FLIS top surface with an imaging magnification factor of about 1:1.

Abstract: A multi-pixel row wafer-scale cluster image sensor chip (WCISC) is proposed. Expressed in X-Y-Z coordinates with its pixel rows along X-axis, the WCISC converts areal image frame (IMFM) into areal image frame signal (AIFS). The WCISC includes multiple imaging pixel rows PXRW1, . . . , PXRWM. Each PXRWi has photoelectrical sensing elements spanning pixel row width PRWi and producing a pixel row image signal PRISi. Each PXRWi is offset from PXRW1 by distance XOFSTi and spaced from PXRWi?1 by distance SPi?1,I such that X- and Y-extremities of (PXRW1, . . . , PXRWM) define IMFM. The WCISC is so configured that any image pixel sweeping through IMFM will be sensed by at least one imaging pixel row. In the presence of Y-directional relative motion between WCISC and IMFM and an external electronic imaging controller (EEIC) interfacing with the WCISC, the EEIC can extract all PRISi from WCISC and reconstruct the AIFS.

Abstract: A time delay integration (TDI) based MOS photoelectric pixel sensing circuit (TDIPSC) is proposed. The TDIPSC includes multi-element photoelectric pixel sensor (MEPS) having sub-pixel sensor elements SPSE1, . . . , SPSEM respectively converting a portion of pixel light into sub-pixel photoelectric signals (SPPES1, . . . , SPPESM). The TDIPSC also includes intermediate photoelectric signal accumulators (PESA1, . . . , PESAM) where any PESAk can be switchably coupled to any SPSEj via switching transistors for receiving a corresponding SPPESj from it and accruing an accumulated photoelectric signal ACPESk. A readout circuit (ROC) switchably coupled to any PESAk serves to remove and read the ACPESk. A TDI-sequence controller (TDISC) coupled to the SPSEs, the PESAs and the ROC executes a time sequence of cyclic coupling among them. The TDISC produces, via the ROC, a final time signal SQTS equal to the time delayed summation of the (SPPES1, . . . , SPPESM) with a reduced SNR.

Abstract: An areal active pixel image sensor (AAPS) with programmable row-specific gain is disclosed for converting hyper-spectral light image into video output signal (VOS). The AAPS includes: a) An areal active pixel sensor (APS) array each capable of photoelectrically converting and integrating an incident pixel light into a photoelectric signal through an integration time period TNT with a photoelectric signal gain GPE. b) A video output signal conditioner (VOSC), coupled to the APS array, for multiplexing and amplifying the photoelectric signals into the VOS with an electric signal gain GEE. c) The VOSC further programmably sets at least one of GPE and GEE to be row-specific. Consequently, the AAPS exhibits an overall photoelectric signal gain of GOA=GPE×GEE that is row-specific and it can compensate for image signal distortion caused by non-uniform spectral response of the APS elements during hyper-spectral imaging.

Abstract: A full-width line image-sensing head (FLIH) is proposed for, expressed in X-Y-Z coordinates, converting a pixel line image (PLI) of length LPL along X-direction into a line image signal (LIS). The FLIH includes a full-width linear image sensor (FLIS) of length LIS along X-direction and displaced from the PLI along Z-direction by an imaging distance DIMG for converting an incident line image (ILI) impinging upon its FLIS top surface into the LIS. Where LIS is about equal to LPL. The FLIH also has a full-width linear rod lens (FLRL) of length LRL along X-direction and displaced from the PLI in Z-direction by a working distance DWKG. Where LRL is about equal to LPL and DWKG is selected such that the PLI gets focused by the FLRL into the ILI at the FLIS top surface with an imaging magnification factor of about 1:1.

Abstract: An areal active pixel image sensor (AAPS) with programmable row-specific gain is disclosed for converting hyper-spectral light image into video output signal (VOS). The AAPS includes: a) An areal active pixel sensor (APS) array each capable of photoelectrically converting and integrating an incident pixel light into a photoelectric signal through an integration time period TNT with a photoelectric signal gain GPE. b) A video output signal conditioner (VOSC), coupled to the APS array, for multiplexing and amplifying the photoelectric signals into the VOS with an electric signal gain GEE. c) The VOSC further programmably sets at least one of GPE and GEE to be row-specific. Consequently, the AAPS exhibits an overall photoelectric signal gain of GOA=GPE×GEE that is row-specific and it can compensate for image signal distortion caused by non-uniform spectral response of the APS elements during hyper-spectral imaging.

Abstract: A configurable, compact multi-resolution linear image sensor array is disclosed. The multi-resolution image sensor array employs a spatial array of photoelectric sites with each site having an image output terminal and a cluster of switched photo-detector elements. To effect a high quality snapshot operation mode for a high pixel count array, a transfer control switch is added bridging each photo-detector element and its correspondingly connected negative input terminal of an operational amplifier to form an active pixel sensor circuit. To minimize a reset kTC noise associated with numerous traditional active pixel sensor circuits, an in-pixel KTC noise-correlated correlated multiple sampling (CMS) circuitry is also proposed to replace an otherwise traditional correlated double sampling (CDS) circuitry.

Abstract: An inverting amplifying circuit for outputting an inversion of an input with good linearity, having an inverter circuit, a feedback capacitance, an input capacitance, a first refresh switch, a second refresh switch, a sleep switch, and a first cutoff switch. A sleep voltage is input through the sleep switch to the inverter circuit for minimizing the electrical power consumption. The sleep switch connects a terminal of the inverter circuit directly to ground when in a sleep mode. The first cut off switch is connected between an output of the inverter circuit and an output of the inverting amplifying circuit.

Abstract: A small sensor circuit with reducible electric power consumption is formed by connecting inverting amplifiers comprised of CMOS inverters connected in an odd number of stages, in series to guarantee the linearity of the relationship between inputs and outputs, and connecting an impedance as a sensor between the inputs and outputs, or to an input.

Abstract: An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.