Patents by Inventor Shengming ZHOU

Shengming ZHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616030
    Abstract: A method for making a three-dimensional (3-D) module includes the steps of: A) forming a laminate of alternate ceramic tape layers and internal electrode layers on a substrate; B) etching said laminate to form first and second capacitor stacks at said first and second locations; C) firing said first and second capacitor stacks integrally; D) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 28, 2023
    Assignee: Southern University of Science and Technology
    Inventors: Guobiao Zhang, Hongyu Yu, Shengming Zhou, Yuejin Guo, Kai Chen, Yida Li, Jun Lan
  • Publication number: 20220084961
    Abstract: A method for making a three-dimensional (3-D) module includes the steps of: A) forming a laminate of alternate ceramic tape layers and internal electrode layers on a substrate; B) etching said laminate to form first and second capacitor stacks at said first and second locations; C) firing said first and second capacitor stacks integrally; D) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 17, 2022
    Applicant: Southern University of Science and Technology
    Inventors: Guobiao ZHANG, Hongyu YU, Shengming ZHOU, Yuejin GUO, Kai CHEN, Yida LI, Jun LAN
  • Patent number: 11217542
    Abstract: A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: January 4, 2022
    Assignee: Southern University of Science and Technology
    Inventors: Guobiao Zhang, Hongyu Yu, Yuejin Guo, Shengming Zhou, Guoxing Zhang, Guangzhao Liu, Mingtao Hu, Wang Zhang
  • Patent number: 11170863
    Abstract: The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAMMB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 9, 2021
    Assignee: Southern University of Science and Technology
    Inventors: Guobiao Zhang, Yida Li, Xiaodong Xiang, Hongyu Yu, Yuejin Guo, Shengming Zhou, Guoxing Zhang, Guangzhao Liu, Mingtao Hu, Wang Zhang, Mei Shen
  • Publication number: 20210013162
    Abstract: A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 14, 2021
    Applicant: Southern University of Science and Technology
    Inventors: Guobiao ZHANG, Hongyu YU, Yuejin GUO, Shengming ZHOU, Guoxing ZHANG, Guangzhao LIU, Mingtao HU, Wang ZHANG
  • Publication number: 20200350030
    Abstract: The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAMMB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.
    Type: Application
    Filed: July 6, 2020
    Publication date: November 5, 2020
    Applicant: Southern University of Science and Technology
    Inventors: Guobiao ZHANG, Hongyu YU, Yuejin GUO, Shengming ZHOU, Guoxing ZHANG, Guangzhao LIU, Mingtao HU, Wang ZHANG, Mei Shen, Yida Li, Xiaodong Xiang